Tootfinder

Just kinda thinking out loud here, don't have a solution or architecture in mind: I really want a better solution for high speed FPGA / ASIC protocol design and debug.
In particular:
1) Using scopehal protocol captures as stimuli for a virtual DUT (i.e. decoded 8b10b of PCIe or something into RTL simulator, pretending to be a SERDES)

TurboFuzz: FPGA Accelerated Hardware Fuzzing for Processor Agile Verification
Yang Zhong, Haoran Wu, Xueqi Li, Sa Wang, David Boland, Yungang Bao, Kan Shi
https://arxiv.org/abs/2509.10400

TurboFuzz: FPGA Accelerated Hardware Fuzzing for Processor Agile Verification
Verification is a critical process for ensuring the correctness of modern processors. The increasing complexity of processor designs and the emergence of new instruction set architectures (ISAs) like RISC-V have created demands for more agile and efficient verification methodologies, particularly regarding verification efficiency and faster coverage convergence. While simulation-based approaches now attempt to incorporate advanced software testing techniques such as fuzzing to improve coverage,…

High-Parallel FPGA-Based Discrete Simulated Bifurcation for Large-Scale Optimization
Fabrizio Orlando, Deborah Volpe, Giacomo Orlandi, Mariagrazia Graziano, Fabrizio Riente, Marco Vacca
https://arxiv.org/abs/2510.12407

High-Parallel FPGA-Based Discrete Simulated Bifurcation for Large-Scale Optimization
Combinatorial Optimization (CO) problems exhibit exponential complexity, making their resolution challenging. Simulated Adiabatic Bifurcation (aSB) is a quantum-inspired algorithm to obtain approximate solutions to largescale CO problems written in the Ising form. It explores the solution space by emulating the adiabatic evolution of a network of Kerr-nonlinear parametric oscillators (KPOs), where each oscillator represents a variable in the problem. The optimal solution corresponds to the grou…

Low Latency, High Bandwidth Streaming of Experimental Data with EJFAT
Ilya Baldin, Michael Goodrich, Vardan Gyurjyan, Graham Heyes, Derek Howard, Yatish Kumar, David Lawrence, Brad Sawatzky, Stacey Sheldon, Carl Timmer
https://arxiv.org/abs/2510.12597

Low Latency, High Bandwidth Streaming of Experimental Data with EJFAT
Thomas Jefferson National Accelerator Facility (JLab) has partnered with Energy Sciences Network (ESnet) to define and implement an edge to compute cluster computational load balancing acceleration architecture. The ESnet-JLab FPGA Accelerated Transport (EJFAT) architecture focuses on FPGA acceleration to address compression, fragmentation, UDP packet destination redirection (Network Address Translation (NAT)) and decompression and reassembly. EJFAT seamlessly integrates edge and cluster comp…

anybody doing Advent of FPGA in Amaranth? https://blog.janestreet.com/advent-of-fpga-challenge-2025/
it seems fun, and, moreover, if you have feedback as a learner I will be more than happy to use it to improve the language

PCIe update: I'm now able to parse incoming InitFC1-* DLLPs and store away the credit counts in a register (which I don't actually use for anything yet), and emit a singular InitFC1-P DLLP of my own
Next step will be writing the rest of the setup logic so I can actually fully bring up VC0, then start sending UpdateFC idle DLLPs at regular intervals to keep the link alive when I'm not sending traffic.

ISAAC: Intelligent, Scalable, Agile, and Accelerated CPU Verification via LLM-aided FPGA Parallelism
Jialin Sun, Yuchen Hu, Dean You, Yushu Du, Hui Wang, Xinwei Fang, Weiwei Shan, Nan Guan, Zhe Jiang
https://arxiv.org/abs/2510.10225

ISAAC: Intelligent, Scalable, Agile, and Accelerated CPU Verification via LLM-aided FPGA Parallelism
Functional verification is a critical bottleneck in integrated circuit development, with CPU verification being especially time-intensive and labour-consuming. Industrial practice relies on differential testing for CPU verification, yet faces bottlenecks at nearly each stage of the framework pipeline: front-end stimulus generation lacks micro-architectural awareness, yielding low-quality and redundant tests that impede coverage closure and miss corner cases. Meanwhile, back-end simulation infra…

Optimised neural networks for online processing of ATLAS calorimeter data on FPGAs
Georges Aad, Raphael Bertrand, Lauri Laatu, Emmanuel Monnier, Arno Straessner, Nairit Sur, Johann C. Voigt
https://arxiv.org/abs/2510.11469

Optimised neural networks for online processing of ATLAS calorimeter data on FPGAs
A study of neural network architectures for the reconstruction of the energy deposited in the cells of the ATLAS liquid-argon calorimeters under high pile-up conditions expected at the HL-LHC is presented. These networks are designed to run on the FPGA-based readout hardware of the calorimeters under strict size and latency constraints. Several architectures, including Dense, Recurrent (RNN), and Convolutional (CNN) neural networks, are optimised using a Bayesian procedure that balances energy …

Does anyone (maybe @… ) have any archival info on DINI Group FPGA boards?
I'm particularly interested in their very silly codenames. The main company front page is available on the wayback machine but since being acquired by Synopsys in 2019 it's no longer around and the wayback machine doesn't seem to have crawled most of their product…

I have an FPGA connected to the STM32 devkit now!
Minimum viable PCIe gateware any% gogogoo

A Scalable FPGA Architecture With Adaptive Memory Utilization for GEMM-Based Operations
Anastasios Petropoulos, Theodore Antonakopoulos
https://arxiv.org/abs/2510.08137 https://…

A Scalable FPGA Architecture With Adaptive Memory Utilization for GEMM-Based Operations
Deep neural network (DNN) inference relies increasingly on specialized hardware for high computational efficiency. This work introduces a field-programmable gate array (FPGA)-based dynamically configurable accelerator featuring systolic arrays, high-bandwidth memory, and UltraRAMs. We present two processing unit (PU) configurations with different computing capabilities using the same interfaces and peripheral blocks. By instantiating multiple PUs and employing a heuristic weight transfer schedu…

Checking on the Ceres FPGA board sims for @… that I had running while I was away. We're looking at a PCIe differential pair layer transition plus AC coupling capacitor.
With no cutout (green trace) response is awful: -3 dB insertion loss at 9.1 GHz, and -10 dB return loss at only 2.8 GHz.
Adding the cutout in the gerbers (blue trace) ma…

PCIe any% speedrun update: LTSSM is in full swing, I've made it all the way to Configuration.LinkWidth.Accept (and improved the ngscopeclient decode for link training in the process).

Enabling Time-Aware Priority Traffic Management over Distributed FPGA Nodes
Alberto Scionti, Paolo Savio, Francesco Lubrano, Federico Stirano, Antonino Nespola, Olivier Terzo, Corrado De Sio, Luca Sterpone
https://arxiv.org/abs/2509.26043

Enabling Time-Aware Priority Traffic Management over Distributed FPGA Nodes
Network Interface Cards (NICs) greatly evolved from simple basic devices moving traffic in and out of the network to complex heterogeneous systems offloading host CPUs from performing complex tasks on in-transit packets. These latter comprise different types of devices, ranging from NICs accelerating fixed specific functions (e.g., on-the-fly data compression/decompression, checksum computation, data encryption, etc.) to complex Systems-on-Chip (SoC) equipped with both general purpose processor…

The MISTer FPGA is overrated crap

Accelerating Dynamic Image Graph Construction on FPGA for Vision GNNs
Anvitha Ramachandran, Dhruv Parikh, Viktor Prasanna
https://arxiv.org/abs/2509.25121 https://

Accelerating Dynamic Image Graph Construction on FPGA for Vision GNNs
Vision Graph Neural Networks (Vision GNNs, or ViGs) represent images as unstructured graphs, achieving state of the art performance in computer vision tasks such as image classification, object detection, and instance segmentation. Dynamic Image Graph Construction (DIGC) builds image graphs by connecting patches (nodes) based on feature similarity, and is dynamically repeated in each ViG layer following GNN based patch (node) feature updates. However, DIGC constitutes over 50% of end to end ViG…

always_comm: An FPGA-based Hardware Accelerator for Audio/Video Compression and Transmission
Rishab Parthasarathy, Akshay Attaluri, Gilford Ting
https://arxiv.org/abs/2509.11503

always_comm: An FPGA-based Hardware Accelerator for Audio/Video Compression and Transmission
We present a design for an extensible video conferencing stack implemented entirely in hardware on a Nexys4 DDR FPGA, which uses the M-JPEG codec to compress video and a UDP networking stack to communicate between the FPGA and the receiving computer. This networking stack accepts real-time updates from both the video codec and the audio controller, which means that video will be able to be streamed at 30 FPS from the FPGA to a computer. On the computer side, a Python script reads the Ethernet p…

Design and deployment of a fast neural network for measuring the properties of muons originating from displaced vertices in the CMS Endcap Muon Track Finder
Efe Yigitbasi (on behalf of CMS Collaboration)
https://arxiv.org/abs/2509.21062

Design and deployment of a fast neural network for measuring the properties of muons originating from displaced vertices in the CMS Endcap Muon Track Finder
We report on the development, implementation, and performance of a fast neural network used to measure the transverse momentum in the CMS Level-1 Endcap Muon Track Finder. The network aims to improve the triggering efficiency of muons produced in the decays of long-lived particles (LLPs). We implemented it in firmware for a Xilinx Virtex-7 FPGA and deployed it during the LHC Run 3 data-taking in 2023. The new displaced muon triggers that use this algorithm broaden the phase space accessible to …

Development of Deep Neural Network First-Level Hardware Track Trigger for the Belle II Experiment
Y. -X. Liu, T. Koga, H. Bae, Y. Yang, C. Kiesling, F. Meggendorfer, K. Unger, S. Hiesl, T. Forsthofer, A. Ishikawa, Y. Ahn, T. Ferber, I. Haide, G. Heine, C. -L. Hsu, A. Little, H. Nakazawa, M. Neu, L. Reuter, V. Savinov, Y. Unno, J. Yuan, Z. Xu
https://

Development of Deep Neural Network First-Level Hardware Track Trigger for the Belle II Experiment
The Belle II experiment at the SuperKEKB accelerator is designed to explore physics beyond the Standard Model with unprecedented luminosity. As the beam intensity increased, the experiment faced significant challenges due to higher beam-induced background, leading to a high trigger rate and placing limitations on further luminosity increases. To address this problem, we developed trigger logic for tracking using deep neural network (DNN) technology on an FPGA for the Belle II hardware trigger s…

My general experience from looking at a lot of RTL between work and open hardware stuff is that ASIC people seem to be more heavy users of advanced systemverilog features (structs, interfaces, etc) than FPGA people.
I know a lot of FPGA tools historically didn't have great support for these things but unless you're still using ISE or Vivado 2017 there's no excuse.
Anyone else see this trend too?

Development of BPM electronics for PIP-II at Fermilab
Shengli Liu (Fermilab, Batavia, USA), Nathan Eddy (Fermilab, Batavia, USA), A. Semenov (Fermilab, Batavia, USA), Brian Fellenz (Fermilab, Batavia, USA)
https://arxiv.org/abs/2509.15388

Development of BPM electronics for PIP-II at Fermilab
This paper presents the uTCA4.0-based BPM electronics for PIP-II, featuring four 250 MSPS ADCs and a Xilinx UltraScale+ MPSoC FPGA with 10 GbE uplink. Design elements include signal conditioning, clock, and thermal management. The FPGA performs signal processing, time tagging, digital down-conversion, and phase drift compensation. Position and phase resolution, and thermal stability - is validated through dedicated testing.

Rare view of my desk during video editing.
With appropriate beverage vessels.

ZynqParrot: A Scale-Down Approach to Cycle-Accurate, FPGA-Accelerated Co-Emulation
Daniel Ruelas-Petrisko, Farzam Gilani, Anoop Mysore Nataraja, Zoe Taylor, Michael Taylor
https://arxiv.org/abs/2509.20543

ZynqParrot: A Scale-Down Approach to Cycle-Accurate, FPGA-Accelerated Co-Emulation
As processors increase in complexity, costs grow even more rapidly, both for functional verification and performance validation. Most often, silicon characterizations comprise simple performance counters, which are aggregated and separated to tell a story. Based on these inferences, performance engineers employ microarchitectural simulation to inspect deeply into the core. Unfortunately, dramatically longer runtimes make simulation infeasible for long workloads. We propose a Scale-Down approa…

SpecMamba: Accelerating Mamba Inference on FPGA with Speculative Decoding
Linfeng Zhong, Songqiang Xu, Huifeng Wen, Tong Xie, Qingyu Guo, Yuan Wang, Meng Li
https://arxiv.org/abs/2509.19873

SpecMamba: Accelerating Mamba Inference on FPGA with Speculative Decoding
The growing demand for efficient long-sequence modeling on edge devices has propelled widespread adoption of State Space Models (SSMs) like Mamba, due to their superior computational efficiency and scalability. As its autoregressive generation process remains memory-bound, speculative decoding has been proposed that incorporates draft model generation and target model verification. However, directly applying speculative decoding to SSMs faces three key challenges: (1) hidden state backtracking …

A Resource-Driven Approach for Implementing CNNs on FPGAs Using Adaptive IPs
Philippe Magalh\~aes (LabHC), Virginie Fresse (LabHC), Beno\^it Suffran (LabHC), Olivier Alata (LabHC)
https://arxiv.org/abs/2510.02990

A Resource-Driven Approach for Implementing CNNs on FPGAs Using Adaptive IPs
The increasing demand for real-time, low-latency artificial intelligence applications has propelled the use of Field-Programmable Gate Arrays (FPGAs) for Convolutional Neural Network (CNN) implementations. FPGAs offer reconfigurability, energy efficiency, and performance advantages over GPUs, making them suitable for edge devices and embedded systems. This work presents a novel library of resource-efficient convolution IPs designed to automatically adapt to the available FPGA resources. Develop…

Bridging Simulation and Silicon: A Study of RISC-V Hardware and FireSim Simulation
Atanu Barai, Kamalavasan Kamalakkannan, Patrick Diehl, Maxim Moraru, Jered Dominguez-Trujillo, Howard Pritchard, Nandakishore Santhi, Farzad Fatollahi-Fard, Galen Shipman
https://arxiv.org/abs/2509.18472

Xilinx XC6SLX25 (Samsung 45nm) from a previous decap run that I had to come back and finish because it was still stuck to the substrate.
A few light scratches in top passivation. These big BGAs need a lot of handling to peel back layers of fiberglass so acid can get in, which increases damage risk. Using fuming nitric usually you don't need that but I don't want it in my house :P
You can't see a whole lot here except the GTP. But if you compare this to the abstracted …

SuperUROP: An FPGA-Based Spatial Accelerator for Sparse Matrix Operations
Rishab Parthasarathy
https://arxiv.org/abs/2509.11529 https://arxiv.org/pdf/2509.…

SuperUROP: An FPGA-Based Spatial Accelerator for Sparse Matrix Operations
Solving sparse systems of linear equations is a fundamental problem in the field of numerical methods, with applications spanning from circuit design to urban planning. These problems can have millions of constraints, such as when laying out transistors on a circuit, or trying to optimize traffic light timings, making fast sparse solvers extremely important. However, existing state-of-the-art software-level solutions for solving sparse linear systems, termed iterative solvers, are extremely ine…

Open-source Stand-Alone Versatile Tensor Accelerator
Anthony Faure-Gignoux, Kevin Delmas, Adrien Gauffriau, Claire Pagetti
https://arxiv.org/abs/2509.19790 https://

Open-source Stand-Alone Versatile Tensor Accelerator
Machine Learning (ML) applications demand significant computational resources, posing challenges for safety-critical domains like aeronautics. The Versatile Tensor Accelerator (VTA) is a promising FPGA-based solution, but its adoption was hindered by its dependency on the TVM compiler and by other code non-compliant with certification requirements. This paper presents an open-source, standalone Python compiler pipeline for the VTA, developed from scratch and designed with certification requirem…

Replaced article(s) found for cs.AR. https://arxiv.org/list/cs.AR/new
[1/1]:
- Holistic Optimization Framework for FPGA Accelerators
St\'ephane Pouget, Michael Lo, Louis-No\"el Pouchet, Jason Cong