Tootfinder

With the emergence of more processors with 64 cores or more, I'm thinking more about whether it makes sense to implement a hypercube virtualised on a single chip with a single vector of memory, or as a literal hypercube of 64 (say) RP2350s. I understand the problems of transferring data across a hypercube, but I don't have a good feeling of how the bus contention on a multicore processor scales. What should I read?

Implementing post scarcity hardware
Prototype work towards building a post-scarcity software system

came up with an alignment chart that can only be expressed as a hypercube. for your sanity i will not be displaying it on this medium