Tootfinder

from my link log —
strlcpy and how CPUs can defy common sense.
https://nrk.neocities.org/articles/cpu-vs-common-sense
saved 2024-07-25

Vollständig gefälschte CPUs jetzt auch als "Ryzen 9800X3D"
In den USA ist ein Fake von AMDs Topseller aufgetaucht, der nach bekanntem Muster hergestellt wurde und mangels Dies funktionslos ist.

Meh. Böse Hitze.

This https://arxiv.org/abs/2409.04668 has been replaced.
initial toot: https://mastoxiv.page/@ar…

Performance Portable Monte Carlo Neutron Transport in MCDC via Numba
Finding a software engineering approach that allows for portability, rapid development, and open collaboration for high-performance computing on GPUs and CPUs is a challenge. We implement a portability scheme using the Numba compiler for Python in Monte Carlo / Dynamic Code (MC/DC), a new neutron transport application for rapidly developing Monte Carlo. Using this scheme, we have built MC/DC as an application that can run as a pure Python, compiled CPU, or compiled GPU solver. In GPU mode, we u…

TEMPEST-LoRa: Cross-Technology Covert Communication
Xieyang Sun, Yuanqing Zheng, Wei Xi, Zuhao Chen, Zhizhen Chen, Han Hao, Zhiping Jiang, Sheng Zhong
https://arxiv.org/abs/2506.21069

TEMPEST-LoRa: Cross-Technology Covert Communication
Electromagnetic (EM) covert channels pose significant threats to computer and communications security in air-gapped networks. Previous works exploit EM radiation from various components (e.g., video cables, memory buses, CPUs) to secretly send sensitive information. These approaches typically require the attacker to deploy highly specialized receivers near the victim, which limits their real-world impact. This paper reports a new EM covert channel, TEMPEST-LoRa, that builds on Cross-Technology …

Evaluating the impact of the L3 cache size of AMD EPYC CPUs on the performance of CFD applications
Marcin Lawenda, {\L}ukasz Szustak, L\'aszl\'o K\"ornyei, Flavio Cesar Cunha Galeazzo, Pawe{\l} Bratek
https://arxiv.org/abs/2505.17934

Evaluating the impact of the L3 cache size of AMD EPYC CPUs on the performance of CFD applications
In this work, the authors focus on assessing the impact of the AMD EPYC processor architecture on the performance of CFD applications. Several generations of architectures were analyzed, such as Rome, Milan, Milan X, Genoa, Genoa X and Bergamo, characterized by a different number of cores (64-128), L3 cache size (256 - 1152 MB) and RAM type (8-channel DDR4 or 12-channel DDR5). The research was conducted based on the OpenFOAM application using two memory-bound models: motorBike and Urban Air Pol…

Large-Scale Simulations of Turbulent Flows using Lattice Boltzmann Methods on Heterogeneous High Performance Computers
Adrian Kummerl\"ander, Fedor Bukreev, Yuji Shimojima, Shota Ito, Mathias J. Krause
https://arxiv.org/abs/2506.21804

Large-Scale Simulations of Turbulent Flows using Lattice Boltzmann Methods on Heterogeneous High Performance Computers
Current GPU-accelerated supercomputers promise to enable large-scale simulations of turbulent flows. Lattice Boltzmann Methods (LBM) are particularly well-suited to fulfilling this promise due to their intrinsic compatibility with highly parallel execution on both SIMD CPUs and GPUs. A novel LBM scheme for wall-modeled LES in complex geometries is described with a special focus on the efficient implementation in the open source LBM framework OpenLB. Detailed scalability results are provided for…

Is there a way to get hardware accelerated #VP9 support on #Skylake era #intel CPUs? Best I can tell, there's an abandoned Intel-hybrid driver with partial support that Intel doesn't want to bring…

PUL: Pre-load in Software for Caches Wouldn't Always Play Along
Arthur Bernhardt, Sajjad Tamimi, Florian Stock, Andreas Koch, Ilia Petrov
https://arxiv.org/abs/2506.16976

PUL: Pre-load in Software for Caches Wouldn't Always Play Along
Memory latencies and bandwidth are major factors, limiting system performance and scalability. Modern CPUs aim at hiding latencies by employing large caches, out-of-order execution, or complex hardware prefetchers. However, software-based prefetching exhibits higher efficiency, improving with newer CPU generations. In this paper we investigate software-based, post-Moore systems that offload operations to intelligent memories. We show that software-based prefetching has even higher potential i…

Jakby ktoś miał problem z sieciowkami na najnowszym ubuntu serwer to polecam sprawdzic kernel:
https://bugs.launchpad.net/ubuntu/ source/linux/ bug/2098961
mi dopiero zadzialal downgrade na kernel 6.8.0-47-generic ... i sieciowka virtio dziala, a na e1…

ScalableHD: Scalable and High-Throughput Hyperdimensional Computing Inference on Multi-Core CPUs
Dhruv Parikh, Viktor Prasanna
https://arxiv.org/abs/2506.09282

ScalableHD: Scalable and High-Throughput Hyperdimensional Computing Inference on Multi-Core CPUs
Hyperdimensional Computing (HDC) is a brain-inspired computing paradigm that represents and manipulates information using high-dimensional vectors, called hypervectors (HV). Traditional HDC methods, while robust to noise and inherently parallel, rely on single-pass, non-parametric training and often suffer from low accuracy. To address this, recent approaches adopt iterative training of base and class HVs, typically accelerated on GPUs. Inference, however, remains lightweight and well-suited fo…

CarbonSet: A Dataset to Analyze Trends and Benchmark the Sustainability of CPUs and GPUs
Jiajun Hu, Chetan Choppali Sudarshan, Vidya A. Chhabria, Aman Arora
https://arxiv.org/abs/2506.10373

CarbonSet: A Dataset to Analyze Trends and Benchmark the Sustainability of CPUs and GPUs
Over the years, the chip industry has consistently developed high-performance processors to address the increasing demands across diverse applications. However, the rapid expansion of chip production has significantly increased carbon emissions, raising critical concerns about environmental sustainability. While researchers have previously modeled the carbon footprint (CFP) at both system and processor levels, a holistic analysis of sustainability trends encompassing the entire chip lifecycle r…

Fun post: Dave Farquhar, History of #overclocking
#Celeron:
> In 1998, Intel released the Celeron to compete with cheap CPUs from AMD and Cyrix. To make it, they took all of the Level 2 cache off a Pentium II, clocked it at 266 or 300 MHz, and sold it at an AMD-like price. But due to the lack of L2 cache, it was slower than a previous-generation Pentium running at 233 MHz, let alone an AMD or Cyrix chip running at 266 or 300 MHz.
>
> But the L2 cache was the Pentium II’s limiting factor in overclocking. So a 266 MHz Celeron ran happily at 400 MHz, or potentially even 450 MHz, the same speed as the fastest Pentium II at the time. It was slower than a Pentium II at the same speed, but it worked well for 3D gaming.
>
> But the only people who bought those Celerons were overclockers and people who didn’t know anything about computers. […]

from my link log —
Distance-based ISA for efficient register renaming.
https://www.sigarch.org/distance-based-isa-for-efficient-register-management/
saved 2025-06-04

Distance-Based ISA for Efficient Register Management
CPU cores have become significantly wider over the past decade. Ten years ago, the highest-performance CPUs could decode only up to four instructions simultaneously and execute up to eight instruct…

Efficient vectorized evaluation of Gaussian AO integrals on modern central processing units
Andrey Asadchev, Edward F. Valeev
https://arxiv.org/abs/2506.12501

Efficient vectorized evaluation of Gaussian AO integrals on modern central processing units
We report an implementation of the McMurchie-Davidson evaluation scheme for 1- and 2-particle Gaussian AO integrals designed for efficient execution on modern central processing units (CPUs) with Single Instruction Multiple Data (SIMD) instruction sets. Like in our recent MD implementation for graphical processing units (GPUs) [J. Chem. Phys. 160, 244109 (2024)], variable-sized batches of shellsets of integrals are evaluated at a time. By optimizing for the floating point instruction throughput…

ShyLU node: On-node Scalable Solvers and Preconditioners Recent Progresses and Current Performance
Ichitaro Yamazaki, Nathan Ellingwood, Sivasankaran Rajamanickam
https://arxiv.org/abs/2506.05793

ShyLU node: On-node Scalable Solvers and Preconditioners Recent Progresses and Current Performance
ShyLU-node is an open-source software package that implements linear solvers and preconditioners on shared-memory multicore CPUs or on a GPU. It is part of the Trilinos software framework and designed to provide a robust and efficient solution of large-scale linear systems from real-world applications on the current and emerging computers. In this paper, we discuss two sparse direct solvers, Basker and Tacho, and an algebraic preconditioner, FastILU, in ShyLU-node package. These ShyLU solvers a…

Capsule: Efficient Player Isolation for Datacenters
Zhouheng Du, Nima Davari, Li Li, Nodir Kodirov
https://arxiv.org/abs/2506.11483 https://

Capsule: Efficient Player Isolation for Datacenters
Cloud gaming is increasingly popular. A challenge for cloud provider is to keep datacenter utilization high: a non-trivial task due to application variety. These applications come in different shapes and sizes. So do cloud datacenter resources, e.g., CPUs, GPUs, NPUs. Part of the challenge stems from game engines being predominantly designed to run only one player. One player in a lightweight game might utilize only a fraction of the cloud server GPU. The remaining GPU capacity will be left u…

A4: Microarchitecture-Aware LLC Management for Datacenter Servers with Emerging I/O Devices
Haneul Park, Jiaqi Lou, Sangjin Lee, Yifan Yuan, Kyoung Soo Park, Yongseok Son, Ipoom Jeong, Nam Sung Kim
https://arxiv.org/abs/2506.11329

A4: Microarchitecture-Aware LLC Management for Datacenter Servers with Emerging I/O Devices
In modern server CPUs, the Last-Level Cache (LLC) serves not only as a victim cache for higher-level private caches but also as a buffer for low-latency DMA transfers between CPU cores and I/O devices through Direct Cache Access (DCA). However, prior work has shown that high-bandwidth network-I/O devices can rapidly flood the LLC with packets, often causing significant contention with co-running workloads. One step further, this work explores hidden microarchitectural properties of the Intel Xe…

Dense Associative Memory in a Nonlinear Optical Hopfield Neural Network
Khalid Musa, Santosh Kumar, Michael Katidis, Yu-Ping Huang
https://arxiv.org/abs/2506.07849

Dense Associative Memory in a Nonlinear Optical Hopfield Neural Network
Modern Hopfield Neural Networks (HNNs), also known as Dense Associative Memories (DAMs), enhance the performance of simple recurrent neural networks by leveraging the nonlinearities in their energy functions. They have broad applications in combinatorial optimization, high-capacity memory storage, deep learning transformers, and correlated pattern recognition. Thus far, research on DAMs has been primarily theoretical, with implementations limited to CPUs and GPUs. In this work, for the first ti…

JAX-LaB: A High-Performance, Differentiable, Lattice Boltzmann Library for Modeling Multiphase Fluid Dynamics in Geosciences and Engineering
Piyush Pradhan, Pierre Gentine, Shaina Kelly
https://arxiv.org/abs/2506.17713

JAX-LaB: A High-Performance, Differentiable, Lattice Boltzmann Library for Modeling Multiphase Fluid Dynamics in Geosciences and Engineering
We present JAX-LaB, a differentiable, Python-based Lattice Boltzmann library for simulating multiphase and multiphysics flows in hydrologic, geologic, and engineered porous media. Built as an extension of the XLB library, JAX-LaB utilizes JAX for computations and offers a performant, hardware-agnostic implementation that integrates seamlessly with machine learning workflows and scales efficiently across CPUs, GPUs, and distributed systems. Multiphase interactions are modeled using the Shan-Chen…

Is Sparse Matrix Reordering Effective for Sparse Matrix-Vector Multiplication?
Omid Asudeh, Sina Mahdipour Saravani, Gerald Sabin, Fabrice Rastello, P Sadayappan
https://arxiv.org/abs/2506.10356

Is Sparse Matrix Reordering Effective for Sparse Matrix-Vector Multiplication?
This work evaluates the impact of sparse matrix reordering on the performance of sparse matrix-vector multiplication across different multicore CPU platforms. Reordering can significantly enhance performance by optimizing the non-zero element patterns to reduce total data movement and improve the load-balancing. We examine how these gains vary over different CPUs for different reordering strategies, focusing on both sequential and parallel execution. We address multiple aspects, including appro…

VecFlow: A High-Performance Vector Data Management System for Filtered-Search on GPUs
Jingyi Xi, Chenghao Mo, Benjamin Karsin, Artem Chirkin, Mingqin Li, Minjia Zhang
https://arxiv.org/abs/2506.00812

VecFlow: A High-Performance Vector Data Management System for Filtered-Search on GPUs
Vector search and database systems have become a keystone component in many AI applications. While many prior research has investigated how to accelerate the performance of generic vector search, emerging AI applications require running more sophisticated vector queries efficiently, such as vector search with attribute filters. Unfortunately, recent filtered-ANNS solutions are primarily designed for CPUs, with few exploration and limited performance of filtered-ANNS that take advantage of the m…

On the Performance of Cloud-based ARM SVE for Zero-Knowledge Proving Systems
Dumitrel Loghin, Shuang Liang, Shengwei Liu, Xiong Liu, Pingcheng Ruan, Zhigang Ye
https://arxiv.org/abs/2506.09505

On the Performance of Cloud-based ARM SVE for Zero-Knowledge Proving Systems
Zero-knowledge proofs (ZKP) are becoming a gold standard in scaling blockchains and bringing Web3 to life. At the same time, ZKP for transactions running on the Ethereum Virtual Machine require powerful servers with hundreds of CPU cores. The current zkProver implementation from Polygon is optimized for x86-64 CPUs by vectorizing key operations, such as Merkle tree building with Poseidon hashes over the Goldilocks field, with Advanced Vector Extensions (AVX and AVX512). With these optimizations…

Large Processor Chip Model
Kaiyan Chang, Mingzhi Chen, Yunji Chen, Zhirong Chen, Dongrui Fan, Junfeng Gong, Nan Guo, Yinhe Han, Qinfen Hao, Shuo Hou, Xuan Huang, Pengwei Jin, Changxin Ke, Cangyuan Li, Guangli Li, Huawei Li, Kuan Li, Naipeng Li, Shengwen Liang, Cheng Liu, Hongwei Liu, Jiahua Liu, Junliang Lv, Jianan Mu, Jin Qin, Bin Sun, Chenxi Wang, Duo Wang, Mingjun Wang, Ying Wang, Chenggang Wu, Peiyang Wu, Teng Wu, Xiao Xiao, Mengyao Xie, Chenwei Xiong, Ruiyuan Xu, Mingyu Yan, Xiaoc…

Large Processor Chip Model
Computer System Architecture serves as a crucial bridge between software applications and the underlying hardware, encompassing components like compilers, CPUs, coprocessors, and RTL designs. Its development, from early mainframes to modern domain-specific architectures, has been driven by rising computational demands and advancements in semiconductor technology. However, traditional paradigms in computer system architecture design are confronting significant challenges, including a reliance on…

This https://arxiv.org/abs/2505.07112 has been replaced.
initial toot: https://mastoxiv.page/@arXiv_csAR_…

Efficient Implementation of RISC-V Vector Permutation Instructions
RISC-V CPUs leverage the RVV (RISC-V Vector) extension to accelerate data-parallel workloads. In addition to arithmetic operations, RVV includes powerful permutation instructions that enable flexible element rearrangement within vector registers --critical for optimizing performance in tasks such as matrix operations and cryptographic computations. However, the diverse control mechanisms of these instructions complicate their execution within a unified datapath while maintaining the fixed-laten…