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@NFL@darktundra.xyz
2025-12-23 11:45:56

Colts QB Philip Rivers on performance vs. 49ers: 'There’s no prize for losing' nfl.com/news/colts-qb-philip-r

@burger_jaap@mastodon.social
2026-02-06 19:25:44

This is a good commentary on the news that Stellantis is writing down €22 billion and blaming customers for not buying its electric cars. However, Stellantis has actually been slow to build and offer electric cars. If they don't offer them, how can customers be expected to buy them?

@arXiv_csDS_bot@mastoxiv.page
2026-02-10 10:09:16

Prune, Don't Rebuild: Efficiently Tuning $\alpha$-Reachable Graphs for Nearest Neighbor Search
Tian Zhang, Ashwin Padaki, Jiaming Liang, Zack Ives, Erik Waingarten
arxiv.org/abs/2602.08097 arxiv.org/pdf/2602.08097 arxiv.org/html/2602.08097
arXiv:2602.08097v1 Announce Type: new
Abstract: Vector similarity search is an essential primitive in modern AI and ML applications. Most vector databases adopt graph-based approximate nearest neighbor (ANN) search algorithms, such as DiskANN (Subramanya et al., 2019), which have demonstrated state-of-the-art empirical performance. DiskANN's graph construction is governed by a reachability parameter $\alpha$, which gives a trade-off between construction time, query time, and accuracy. However, adaptively tuning this trade-off typically requires rebuilding the index for different $\alpha$ values, which is prohibitive at scale. In this work, we propose RP-Tuning, an efficient post-hoc routine, based on DiskANN's pruning step, to adjust the $\alpha$ parameter without reconstructing the full index. Within the $\alpha$-reachability framework of prior theoretical works (Indyk and Xu, 2023; Gollapudi et al., 2025), we prove that pruning an initially $\alpha$-reachable graph with RP-Tuning preserves worst-case reachability guarantees in general metrics and improved guarantees in Euclidean metrics. Empirically, we show that RP-Tuning accelerates DiskANN tuning on four public datasets by up to $43\times$ with negligible overhead.
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@arXiv_physicsinsdet_bot@mastoxiv.page
2026-02-03 09:12:46

PCIe400 generic readout board qualification test
Kevin Arnaud, Antoine Back, Daniel Charlet, Gabriel Degret, Luigi Del Buono, Paolo Durante, Amaury Hervo, Fr\'ed\'eric Hachon, Xavier Lafay, Julien Langou\"et, Renaud Le Gac, Jea-Luc Meunier, Jean-Marc Nappa, Costy Nassif Mattar, Christophe Renard, Guillaume Vouters
arxiv.org/abs/2602.01422 arxiv.org/pdf/2602.01422 arxiv.org/html/2602.01422
arXiv:2602.01422v1 Announce Type: new
Abstract: The PCIe400 is a generic board for high-throughput data acquisition systems in high energy physics experiments. Its purpose is to interface up to 48 bidirectional links, supporting custom protocols at 1 to 26 Gbit/s, to modern commercial back-end links providing 400 Gbit/s bandwidth. It also targets clock distribution with phase determinism below 10 ps peak-to-peak. It has been designed for LHCb LS3 enhancement upgrade with experimental features to prepare LHCb Upgrade II, foreseeing an aggregated throughput of 200 Tbit/s. However, its versatility allows it to be used in several experimental environments. The board embeds Altera's flagship Agilex 7 M-series FPGA with a PCIe Gen 5 interface and an experimental QSFP112 serial interface. We present the results of qualification tests performed on prototype boards and the challenges encountered to meet specifications. Section 1 describes board-level validation, including power-up behavior and peripheral access. Section 2 focuses on high-bandwidth interface qualification through BER measurements. Finally, Section 3 investigates phase determinism in Agilex transceivers, a key requirement for precise clock distribution.
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