2025-12-14 18:41:07
A patch for optimizing #GIMP 3.0 to mimic the position of Adobe Photoshop tools, maximize space on the canvas,
get shortcuts similar to the ones in Photoshop...
https://github.com/Diolinux/PhotoGIMP…
A patch for optimizing #GIMP 3.0 to mimic the position of Adobe Photoshop tools, maximize space on the canvas,
get shortcuts similar to the ones in Photoshop...
https://github.com/Diolinux/PhotoGIMP…
PIC12F683 SRAM row address decoding.
The physical memory array is 32 x 32 bitcells (1 kbit / 128 bytes), logically 32 rows x 4-way column mux x 8 bit data bus.
The row logic decodes the 5-bit row address into ten one-hot signals for X and !X. Each wordline is driven by a 5-input AND gate, where each row selects a different one of the 32 combinations.
The PIC12F683 uses a very straightforward address order with MSB at left and LSB at right, and addresses counting in what see…
Re all the people who asked "how much ram is a lot" the other day...
This is why I have to be careful on my office workstation with "only" 192GB. Had I not checked and closed ImageJ before saving the file I was working on in GIMP, I would have OOM'd (it peaked at 162.5 GB total usage during the save, adding in the 50.6 that ImageJ was using I'd be at 213.1)
This rig is from 2017 and is still going strong so I'm in no rush to replace it, but when I …
Eureka moment on the EEPROM, I think I just found the column address lines. Need to trace a bit more out to be 100%.
If so, I'll have to rearrange a bunch of schematic and rename a bunch of signals (the slow and arduous way because GIMP and KiCAD don't sync and GIMP has no idea what a netlist is, lol)
RE: https://social.linux.pizza/@midtsveen/114569187488352747
"made with gimp"
Working on reversing for the EEPROM chapter of the PIC12F683 video and I'm working with a 2.5 GB (on disk) XCF file with 125 layers and I still have more tiles to load and align.
Just for this one memory IP (and not even the whole thing).
Somewhat surprisingly, GIMP is only using 19.8 GB of RAM editing it.
Filmed and edited another segment of the PIC video (intro to reading standard cell planar CMOS with whiteboard examples plus deconstructing actual photos of an inverter, NAND2, and GDCAP), now an hour 38 minutes.
Still need to do circuit analysis of the SRAM, flash/EEPROM, config fuses, whatever else I might want to dig into, and add some conclusions.