
2025-06-04 18:10:40
FPGA people: how cursed is it if I scramble TX/RX lanes of my transceivers so that e.g. TX lane 0 and RX lane 1 go to a single SFP28?
They're separate clock domains anyway, separate PLL taps. I'm not using the CPLL so that's no factor.
It feels wrong, but I can't think of any reason why it would be? (I've done this before and it worked fine but that was with hacky breakout to SMA setups, not by design on a PCB)