Tootfinder

FPGA people: how cursed is it if I scramble TX/RX lanes of my transceivers so that e.g. TX lane 0 and RX lane 1 go to a single SFP28?
They're separate clock domains anyway, separate PLL taps. I'm not using the CPLL so that's no factor.
It feels wrong, but I can't think of any reason why it would be? (I've done this before and it worked fine but that was with hacky breakout to SMA setups, not by design on a PCB)

from my link log —
Recovering control flow structures from Java bytecode without CFGs.
https://purplesyringa.moe/blog/recovering-control-flow-structures-without-cfgs/
saved 2025-06-06

Recovering control flow structures without CFGs
I’m working on a Java decompiler because I’m not satisfied with the performance of other solutions. I’ve always heard that decompiling JVM bytecode is a solved problem, but I’ve concluded that the decompilation methods used by CFR and Vineflower are hacky, inefficient, and sometimes don’t even work. The existing solutions are haphazard and inadequate compared to alternative approaches. Specifically, I have beef with the control flow extraction strategies employed by most decompilers. …

My JS Krups is resisting netbooting. I see it doing a DHCP discover, and I see Kea responding with an offer, but then it just sends another Discover. Hmph. I can get to the serial console and doing boot net from there doesn't help; none of the keyboard shortcuts for network diag etc seem to work (except the one that displays the help for it...). So I took the flash SIM out and now it boots to Net rather than flash by default; alas with the same DHCP behaviour. Time to try isc-dhcp.…