Also, unlike this one, many of my skeets don’t get here. Something about @… doesn’t pick them all up. Probably bsky is sinking the stuff they determine not interesting or whatever.
I despise algorithmic feeds where I can’t fix my algorithm. @…
And another open FPGA debug IP joins my rapidly growing suite.
These are all portable systemverilog and will run on anything, but the immediate motivation is making up for Efinix's rather lackluster debug tools.
The general concept is basically "CoreSight / ADIv5 for FPGAs". You have a generic transport (so far only UART is implemented) that provides read/write access to an internal APB bus with debug IPs hanging off it.
The debug bridge points to a ROM table …
It’s amazing to realize how British accents no longer seem different to me. I can understand them so much more than I could before and because I consume a lot of British media, I am beginning to not be able to differentiate them from the accents I grew up with.