Tootfinder

A Long Period Stellar-mass #BlackHole Binary in ω Centauri: https://iopscience.iop.org/article/10.3847/2041-8213/ae7a5c -> Hubble discovers first of star cluster’s missing black holes: https://esahubble.org/news/heic2610/ and https://science.nasa.gov/missions/webb/nasas-hubble-discovers-first-of-star-clusters-missing-black-holes/

A flying robot with an explosive payload can fly through some of the most heavily defended airspace on earth, by itself, for like a thousand miles to turn a petrochemical facility into a raging inferno just by comparing what it sees with its camera to the images in its memory banks.
But no one has found a way to peek into a hospital room to find out if an octogenarian Senator from Kentucky has a pulse.
Can we send in a pulse finding drone perhaps for a heart attack damage asses…

The Oldest Stars in the Galaxy Just Weighed In on One of Cosmology's Biggest Arguments - Universe Today https://www.universetoday.com/articles/the-oldest-stars-in-the-galaxy-just-weighed-in-on-one-of-cosmologys-bigges…

The emerging timescale of young #StarClusters regulated by cluster stellar mass: https://www.nature.com/articles/s41550-026-02857-y -> Webb & Hubble find massive star clusters emerge faster: https://www.esa.int/Science_Exploration/Space_Science/Webb/Webb_Hubble_find_massive_star_clusters_emerge_faster

Formal Verification of an Out-of-Order Multiprocessor against an In-Order Weak-Memory ISA
Janggun Lee, Jeehoon Kang
https://arxiv.org/abs/2607.18727 https://arxiv.org/pdf/2607.18727 https://arxiv.org/html/2607.18727
arXiv:2607.18727v1 Announce Type: new
Abstract: Out-of-order multiprocessor is a critical piece of modern hardware, and their verification must solve the following challenges. First, inter-core interleaving, in which the order their reads and writes reach shared memory is unrestricted. Second, intra-core out-of-order execution, in which instructions fire out of program order. The combination of the two yields weak outcomes, which no sequential execution explains, and modern ISA allows such behaviors to account for them. However, the microarchitecture even exhibits excess out-of-order executions, temporarily entering states forbidden by the ISA. While discarded later, such states complicate reasoning about the core in full-system verification. Prior works verify a range of processor designs, while none have performed unbounded verification for out-of-order multiprocessor exhibiting such weak outcomes.
We present the first formal verification of an out-of-order multiprocessor against an in-order, weak-memory ISA. Our key idea is a well-designed core specification, which captures the essence of excess executions in a single list of instructions. Building upon this, we decompose the proof into two steps. The first is a core refinement, proving a core implementation against this specification, abstracting away every microarchitectural state except those necessary to reason about excess executions and the core interface. The second is a system inclusion, serializing the out-of-order memory executions and inter-core interleaving into the ISA, easily removing excess executions thanks to the core specification. All of our proofs are mechanized in Rocq, heavily utilizing large language model (LLM) agents to write proofs automatically.
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