Tootfinder

Structural Completeness in bi-IPC
Rodrigo Nicolau Almeida, Nick Bezhanishvili
https://arxiv.org/abs/2508.05682 https://arxiv.org/pdf/2508.05682

Structural Completeness in bi-IPC
In this note we show that no extension of bi-intuitionistic logic, except for classical logic, is structurally complete; indeed, none of them are passively structurally complete. A direct proof of active structural completeness is given for some simple systems.

ROS 2 Agnocast: Supporting Unsized Message Types for True Zero-Copy Publish/Subscribe IPC
Takahiro Ishikawa-Aso, Shinpei Kato
https://arxiv.org/abs/2506.16882

ROS 2 Agnocast: Supporting Unsized Message Types for True Zero-Copy Publish/Subscribe IPC
Robot applications, comprising independent components that mutually publish/subscribe messages, are built on inter-process communication (IPC) middleware such as Robot Operating System 2 (ROS 2). In large-scale ROS 2 systems like autonomous driving platforms, true zero-copy communication -- eliminating serialization and deserialization -- is crucial for efficiency and real-time performance. However, existing true zero-copy middleware solutions lack widespread adoption as they fail to meet three…

‘Worst-case scenario of famine’ now unfolding in Gaza: Global hunger monitoring system.
https://www.aljazeera.com/news/liveblog/2025/7/29/live-israel-kills-92-in-gaza-in-one-day-as-death-toll-nears-60000?updat…

@… wanted to sanity check something here.
The H7 series UFBGA176 25 package is 0.65mm pitch, 0.29mm diameter solder balls. Their recommended pad diameter is 0.3mm which is odd, per IPC I think you'd normally want an 0.25mm land.
But where things get weird is the 0.8mm TFBGA240 25. It's 0.4mm diameter balls, so I would expect 0.3mm lands but…

Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution
Zexin Fu, Riccardo Tedeschi, Gianmarco Ottavi, Nils Wistoff, C\'esar Fuguet, Davide Rossi, Luca Benini
https://arxiv.org/abs/2505.24363

Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution
Open-source RISC-V cores are increasingly demanded in domains like automotive and space, where achieving high instructions per cycle (IPC) through superscalar and out-of-order (OoO) execution is crucial. However, high-performance open-source RISC-V cores face adoption challenges: some (e.g. BOOM, Xiangshan) are developed in Chisel with limited support from industrial electronic design automation (EDA) tools. Others, like the XuanTie C910 core, use proprietary interfaces and protocols, including…

CrossPL: Evaluating Large Language Models on Cross Programming Language Code Generation
Zhanhang Xiong, Dongxia Wang, Yuekang Li, Xinyuan An, Wenhai Wang
https://arxiv.org/abs/2507.19904

CrossPL: Evaluating Large Language Models on Cross Programming Language Code Generation
As large language models (LLMs) become increasingly embedded in software engineering workflows, a critical capability remains underexplored: generating correct code that enables cross-programming-language (CPL) interoperability. This skill is essential for building complex systems that integrate components written in multiple languages via mechanisms like inter-process communication (IPC). To bridge this gap, we present CrossPL, the first benchmark designed to systematically evaluate LLMs' abil…