No exact results. Similar results found.
@azonenberg@ioc.exchange2025-12-01 01:18:58
Next step on the STM32MP2, now that I have the MMU mostly brought up, is going to be turning on the caches and figuring out how to flush / invalidate cache lines when I'm exchanging data with other cores.
Or maybe it'll be simpler to just add a third level page table and mark some/all of SRAM2 as uncacheable since all of my IPC is happening there?
Either way I need to invalidate and turn the caches on.
I think that's really the last major thing left to do before…
@whitequark@mastodon.social2025-11-22 09:30:53
bots have finally knocked a grebedoc runner offline (one bar per 10s, so this was 71 uncached req/s at its peak)
