2025-12-17 07:15:24
PCIe any% speedrun, day 6: Almost at minimum-viable-baseline-happy-path status!
It's still 2.5 GT/s only, I haven't implemented up-negotiation to 5 GT/s speed yet (or tested that on the SoC side for that matter).
Configuration reads and writes work; they're translated to APB bus transactions and bridged to an APB register block that reports a bunch of hard coded default values and lets you change a few things like BARs.




