Mission accomplished! Still a bunch of rough edges to work out, and I need to build equivalent blocks for other line codings as well as a "generic" ILA that just records waveforms.
But here's a simultaneous cross-trigger of the SERDES ILA and an analog waveform capture of the signal going into the SFP, (manually) deskewed and aligned.
Now imagine extending this to additional debug blocks within the FPGA.
Help I’ve been pinned down and can’t move! #caturday
Happy #caturday Ran across this cat sitting on top of a mailbox on a walk. It very much enjoyed the head scratching.
#catsofmastodon #cat
Equinix, whose stock is up 33% YTD, pushing its market cap to $100B, inks a deal with Nvidia to let customers run their AI models on the Together AI platform (CNBC)
https://www.cnbc.com/2026/09/02/equinix-partners-with-nvidia-carves-niche…