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@azonenberg@ioc.exchange
2025-12-23 01:13:06

Making progress! 344 unrouted. Definitely getting tight, I may have to delete a few of the test points or shrink things in a bit, but I think I can pull it off. It's been a while since I've done a high density 4 layer board instead of my more recent usual 10L with ViP.

KiCAD 3D render of the top side of a dense PCB with connectors along the south side, two BGAs in the north center and east, and a SFP+ cage in the southwest
Underside of the same PCB showing dense trace routing covering much of the back side, plus a significant number of passives down to 0201 size
@azonenberg@ioc.exchange
2026-01-22 22:17:22

Early experimenting with a new-user tutorial for ngscopeclient.
Thoughts?

ngscopeclient showing a speech bubble reading "Add an oscilloscope to your session" on the menu bar, with a tutorial wizard in the main application view prompting the user to add the scope
@azonenberg@ioc.exchange
2026-01-22 05:41:30

Added a scrollable list of errors to the filter graph editor so you can see multiple problems more clearly.
The error message automatically spawns, docked to the south side of the filter graph editor, when an error appears and disappears when the last error is resolved.

Filter graph editor showing a single block outlined in red with a list of missing inputs in a scrollable list below it
@azonenberg@ioc.exchange
2026-01-22 04:50:44

Aaaand this is why I have 40GbE to my desk.
Early test, I need a bunch of optimization to do (multiscope is not as performant as I want I suspect there's mutex issues and/or unnecessary filter graph refreshes).
But here's two thunderscopes hosted on separate machines, each with 10GbE to the core switch, then 40G from there to my workstation.

ngscopeclient showing a FFT and eye pattern from two different ThunderScopes plus an iftop window showing about 15 Gbps of network traffic
@azonenberg@ioc.exchange
2025-12-22 08:13:13

468 nets unrouted. Still have to do the FPGA flash, the power supply, bulk caps for the FPGA, and a few other odds and ends but the entire SoC subsystem is basically routed.
So at this point I can already say definitively that routing the STM32MP2 in TFBGA436 on an OSHPark 4-layer board is extremely doable as long as you aren't trying to max the IOs. Using the DDR may or may not be possible (I'm not trying here) but the internal RAM and HyperRAM are enough for a lot of applicat…

KiCAD layout render of a 4-layer board with a large FPGA at the center, a slightly smaller SoC to the east, a SFP+ in the southwest, and a bunch of floating passives not yet hooked up
@azonenberg@ioc.exchange
2025-10-23 05:10:08

Atmel ATSAMA5D27. Also not my best work, but hey it's a sample I have so might as well photograph it.
It was desoldered from something but I have no idea what the origin was.
siliconprawn.org/map/atmel/ats

Top metal of an IC die with two rings of bond pads, aluminum top layer power/ground grid, and some analog stuff in the southwest
@azonenberg@ioc.exchange
2025-10-23 04:47:58

Xilinx XC6SLX25 (Samsung 45nm) from a previous decap run that I had to come back and finish because it was still stuck to the substrate.
A few light scratches in top passivation. These big BGAs need a lot of handling to peel back layers of fiberglass so acid can get in, which increases damage risk. Using fuming nitric usually you don't need that but I don't want it in my house :P
You can't see a whole lot here except the GTP. But if you compare this to the abstracted …

Top metal image of an FPGA. Not a whole lot visible since the whole die is covered in power/ground grid, except for the GTP SERDES block in the top just left of center
@azonenberg@ioc.exchange
2025-10-23 07:57:41

Xilinx XC7Z010, the first Zynq I've decapped.
Top metal has pretty significant damage because it spent over an hour in the acid to get all of the substrate off, then several fairly aggressive cleaning cycles to remove most of the polyimide (but there's still some golden residue scattered around, I'll try some more cleaning tomorrow to try and get all of it and re-image)
But this die is destined to be stripped to substrate so I can do floorplan analysis, so that's …

Top metal image of an IC die with power/ground routing running north/south in the east 2/3, east/west in the west 1/3, and diagonal in the northwest corner
@azonenberg@ioc.exchange
2026-01-21 05:48:22

Missed the first peak of tonight's show because I was busy showing my wife from the front steps and didn't get my camera set up, lol.
Got a few nice shots from the park before it slowed down too much but got cold and didn't want to be out too late. If it picks up again I might pop outside.

Red and green aurora glow above tree-covered hills  silhouetted against the sky
Green aurora glow lighting up the sky above a tree-lined dirt parking lot
A starry sky, centered on Orion, seen above several tall trees
@azonenberg@ioc.exchange
2025-12-23 03:31:38

RDMA over Catgirl Excitement