Tootfinder

Here are the slides to the talk I gave at @… #LinuxDay today.
https://metaspora.org/riscv-mainline-l…

RV32I in ACL2
Carl Kwan (The University of Texas at Austin)
https://arxiv.org/abs/2507.19009 https://arxiv.org/pdf/2507.19009

RV32I in ACL2
We present a simple ACL2 simulator for the RISC-V 32-bit base instruction set architecture, written in the operational semantics style. Like many other ISA models, our RISC-V state object is a single-threaded object and we prove read-over-write, write-over-write, writing-the-read, and state well-formedness theorems. Unlike some other models, we separate the instruction decoding functions from their semantic counterparts. Accordingly, we verify encoding / decoding functions for each RV32I instru…

from my link log —
CHERI with a Linux on top.
https://lwn.net/SubscriberLink/1037974/903c6f9a42f7782a/
saved 2025-09-26 https://

At the 2025 RISC-V Summit in China, Nvidia says CUDA will now be compatible with RISC-V's instruction set architecture, making RISC-V a viable x86 and Arm rival (Anton Shilov/Tom's Hardware)
https://www.

Nvidia's CUDA platform now supports RISC-V — support brings open source instruction set to AI platforms, joining x86 and Arm
Yet another alternative.

Support Vector Machines Classification on Bendable RISC-V
Polykarpos Vergos, Theofanis Vergos, Florentia Afentaki, Konstantinos Balaskas, Georgios Zervakis
https://arxiv.org/abs/2508.19656

Support Vector Machines Classification on Bendable RISC-V
Flexible Electronics (FE) technology offers uniquecharacteristics in electronic manufacturing, providing ultra-low-cost, lightweight, and environmentally-friendly alternatives totraditional rigid electronics. These characteristics enable a rangeof applications that were previously constrained by the costand rigidity of conventional silicon technology. Machine learning (ML) is essential for enabling autonomous, real-time intelligenceon devices with smart sensing capabilities in everyday objects.…

Bridging Simulation and Silicon: A Study of RISC-V Hardware and FireSim Simulation
Atanu Barai, Kamalavasan Kamalakkannan, Patrick Diehl, Maxim Moraru, Jered Dominguez-Trujillo, Howard Pritchard, Nandakishore Santhi, Farzad Fatollahi-Fard, Galen Shipman
https://arxiv.org/abs/2509.18472

Pedagogically Motivated and Composable Open-Source RISC-V Processors for Computer Science Education
Ian McDougall, Harish Batchu, Michael Davies, Karthikeyan Sankaralingam
https://arxiv.org/abs/2509.20514

Pedagogically Motivated and Composable Open-Source RISC-V Processors for Computer Science Education
While most instruction set architectures (ISAs) are only available to use through the purchase of a restrictive commercial license, the RISC-V ISA presents a free and open-source alternative. Due to this availability, many free and open-source implementations have been developed and can be accessed on platforms such as GitHub. If an open source, easy-to-use, and robust RISC-V implementation could be obtained, it could be easily adapted for pedagogical and amateur use. In this work we accomplish…

Accelerating Gravitational $N$-Body Simulations Using the RISC-V-Based Tenstorrent Wormhole
Jenny Lynn Almerol, Elisabetta Boella, Mario Spera, Daniele Gregori
https://arxiv.org/abs/2509.19294

from my link log —
Performance from architecture: comparing a RISC (MIPS) and a CISC (VAX) with similar hardware organization. (1991)
https://dl.acm.org/doi/abs/10.1145/106974.107003
saved 2025-09-26

X-HEEP: An Open-Source, Configurable and Extendible RISC-V Platform for TinyAI Applications
Simone Machetti, Pasquale Davide Schiavone, Giovanni Ansaloni, Miguel Pe\'on-Quir\'os, David Atienza
https://arxiv.org/abs/2508.16959

X-HEEP: An Open-Source, Configurable and Extendible RISC-V Platform for TinyAI Applications
In this work, we present X-HEEP, an open-source, configurable, and extendible RISC-V platform for ultra-low-power edge applications (TinyAI). X-HEEP features the eXtendible Accelerator InterFace (XAIF), which enables seamless integration of accelerators with varying requirements along with an extensive internal configuration of cores, memory, bus, and peripherals. Moreover, it supports various development flows, including FPGA prototyping, ASIC implementation, and mixed SystemC-RTL modeling, en…