Tootfinder

Final joint on the north frame if the workshop. I cut the mortice horizontally, which was a lot more awkward, but not as awkward as dismantling the whole frame and putting it together again.
Still ill, but I've managed this.

Circuit & Chisel, whose ATXP protocol enables AI agents to make autonomous payments, raised a $19.2M seed led by Primary Venture Partners and ParaFi (Leo Schwartz/Fortune)
https://fortune.com/2025/09/22/stripe-crypto-alum-agentic-ai-payments-cir…

Stripe crypto alum raise $19.2 million to power agentic payments through ATXP protocol
ATXP wants to create the first useful generation of AI agents through its HTTP-like protocol.

Another mortice and its tenon done. Rain, cold, abd strong wind have stopped play for now, and progress on the new workshop is slow. But it is progress.

Nail: Not Another Fault-Injection Framework for Chisel-generated RTL
Robin Sehm, Christian Ewert, Rainer Buchty, Mladen Berekovic, Saleh Mulhem
https://arxiv.org/abs/2508.06344 …

Nail: Not Another Fault-Injection Framework for Chisel-generated RTL
Fault simulation and emulation are essential techniques for evaluating the dependability of integrated circuits, enabling early-stage vulnerability analysis and supporting the implementation of effective mitigation strategies. High-level hardware description languages such as Chisel facilitate the rapid development of complex fault scenarios with minimal modification to the design. However, existing Chisel-based fault injection (FI) frameworks are limited by coarse-grained, instruction-level co…

MemorySim: An RTL-level, timing accurate simulator model for the Chisel ecosystem
Ansh Chaurasia
https://arxiv.org/abs/2508.12636 https://arxiv.org/pdf/250…

MemorySim: An RTL-level, timing accurate simulator model for the Chisel ecosystem
The rapid growth of AI applications has driven increased demand for specialized AI hardware, highlighting critical opportunities within the memory subsystem, which often serves as a performance bottleneck in high-demand workloads such as large language models (LLMs). Existing high-level memory simulators, such as DRAMSim2 and DRAMSim3, offer timing simulations but frequently compromise on correctness or integration at the register-transfer level (RTL). We present MemorySim, an RTL-level memory …

A Hat Full of Sky - Terry Pratchett
> ‘Here is a story to believe,’ she said. ‘Once we were blobs in the sea, and then fishes, and then lizards and rats and then monkeys, and hundreds of things in between. This hand was once a fin, this hand once had claws! In my human mouth I have the pointy teeth of a wolf and the chisel teeth of a rabbit and the grinding teeth of a cow! Our blood is as salty as the sea we used to live in! When we’re frightened the hair on our skins stands up, jus…

Towards An Approach to Identify Divergences in Hardware Designs for HPC Workloads
Doru Thom Popovici, Mario Vega, Angelos Ioannou, Fabien Chaix, Dania Mosuli, Blair Reasoner, Tan Nguyen, Xiaokun Yang, John Shalf
https://arxiv.org/abs/2509.09774

Towards An Approach to Identify Divergences in Hardware Designs for HPC Workloads
Developing efficient hardware accelerators for mathematical kernels used in scientific applications and machine learning has traditionally been a labor-intensive task. These accelerators typically require low-level programming in Verilog or other hardware description languages, along with significant manual optimization effort. Recently, to alleviate this challenge, high-level hardware design tools like Chisel and High-Level Synthesis have emerged. However, as with any compiler, some of the gen…