Tootfinder

"The trick is knowing which tape to use, and young influencers on the social media platform are quick to enter into paid partnerships to sell the one brand of mouth tape you really need."
The Paper-Thin Evidence for Mouth Taping https://www.mcgill.ca/oss/article/critical

Nail: Not Another Fault-Injection Framework for Chisel-generated RTL
Robin Sehm, Christian Ewert, Rainer Buchty, Mladen Berekovic, Saleh Mulhem
https://arxiv.org/abs/2508.06344 …

Nail: Not Another Fault-Injection Framework for Chisel-generated RTL
Fault simulation and emulation are essential techniques for evaluating the dependability of integrated circuits, enabling early-stage vulnerability analysis and supporting the implementation of effective mitigation strategies. High-level hardware description languages such as Chisel facilitate the rapid development of complex fault scenarios with minimal modification to the design. However, existing Chisel-based fault injection (FI) frameworks are limited by coarse-grained, instruction-level co…

New lab acquisition: MinusK 50BM-4 passive vibration isolator.
Going to have to get a more permanent weight to balance it right (there's currently a random steel chisel under the microscope in one corner and a CPU heatsink on top) but it's a huge improvement over the random aluminum plate with sorbothane feet.
Huge improvement in stability. The biggest problem is that changing objectives is now a two hand job, the microscope is floated so well that if i grab the turret th…

MemorySim: An RTL-level, timing accurate simulator model for the Chisel ecosystem
Ansh Chaurasia
https://arxiv.org/abs/2508.12636 https://arxiv.org/pdf/250…

MemorySim: An RTL-level, timing accurate simulator model for the Chisel ecosystem
The rapid growth of AI applications has driven increased demand for specialized AI hardware, highlighting critical opportunities within the memory subsystem, which often serves as a performance bottleneck in high-demand workloads such as large language models (LLMs). Existing high-level memory simulators, such as DRAMSim2 and DRAMSim3, offer timing simulations but frequently compromise on correctness or integration at the register-transfer level (RTL). We present MemorySim, an RTL-level memory …