Alman is a simplified dialect of German designed to reduce the complexity of the language while maintaining mutual intelligibility with Standard German.
It systematically eliminates several complex grammatical features:
🔸Gender System: Uses a single article form for most contexts
🔸Case Markings: Removes most case-based inflections
🔸Noun Declensions: Simplifies noun endings across cases
🔸Job Titles: Eliminates gender-specific forms in occupational titles
The English home page…
Apple korrigiert Hide my Email im dritten Anlauf
Apples Dienst „E-Mail-Adresse verbergen” schaffte das nur schlecht. Die echten Adressen aufzudecken, war simpel.
https://www.heise.de/news/Appl…
from my link log —
Symbolic execution with SymCC: don't interpret, compile!
http://www.s3.eurecom.fr/tools/symbolic_execution/symcc.html
saved 2020-07-08
A Common Sunflower. LA Arboretum, Arcadia, California, USA. August, 2026. OM System OM-1 M.Zuiko 300mm F4 MC14. #laarboretum #flower #sunflower
Arturia MiniFreak wird mit Firmware 5.0 zum Sampler
Arturia bedenkt den Synthesizer MiniFreak nach 15 Monaten mit einem Firmwareupdate. Es ergänzt User-Samples und -Wavetables.
https://www.…
PSEC6: an 8-Channel 40 GSa/s Waveform Sampling ASIC in TSMC 65nm with 10.24 GHz PLL
Ahan Datta, Andrew Arzac, Davide Braga, Gordon Chen, Troy England, Farah Fahim, Henry J. Frisch, Nathan Gehl, Mary Heintz, Sumin Kim, Ava Lalich, Jinseo Park, Nathaniel J. Pastika, Hector D. Rico-Aniles, Paul M. Rubinov, Xiaoran Wang, Y. M. Richmond Yeung
https://arxiv.org/abs/2608.19473 https://arxiv.org/pdf/2608.19473 https://arxiv.org/html/2608.19473
arXiv:2608.19473v1 Announce Type: new
Abstract: Picosecond level timing resolution is a prerequisite capability for improved coincidence matching, time-of-flight measurements, and secondary vertex reconstruction. Here, we present the specification, design, and simulation results for a new Application Specific Integrated Circuit (ASIC), called PSEC6, in the TSMC 65nm process. It features 8 channels, a maximum sampling rate of 40 GSa/s, a buffer length of 204.8 nanoseconds, and a 10.24 GHz Phase Locked Loop (PLL), which is the first of its kind in the 65nm CMOS process. The event readout rate is 32 kHz, with the digitization done by an off-chip Analog-to-Digital Converter (ADC).
Simulations predict a 4.0 GHz analog input bandwidth and 20 mW per channel during sampling; the 10.24 GHz PLL has a predicted jitter of 550 fs RMS at 15.7 mW. The paper describes the sampling architecture, chip signal paths, PLL design, and presents simulation results.
toXiv_bot_toot
Deeper solar wind penetration on the Moon’s farside from noble gas records: #SolarWind striking moon's near side: https://phys.org/news/2026-07-samples-reveal-earth-solar-moon.html
NFL analytics glossary: A simple guide to the complex world of advanced football stats https://www.nytimes.com/athletic/7605384/2026/09/22/nfl-analytics-explainer-guide-glossary-epa-success-rate/
Susan Kare: Wie die Designerin die frühen Mac-Icons prägte
Die Grafikdesignerin Susan Kare gab Einblicke in die Entstehung der frühen Mac-Icons. Sie entwickelte unter anderem den Happy Mac und das CMD-Symbol.
ht…