@EarthOrgUK@mastodon.energyOn the Zanussi ZDS2010 freestanding slimline dishwasher: Review - Read all about how it worked for us and lasted longer than expected (with some TLC), but is sadly barely more efficient than the old model. - https://www.earth.org.uk/note-on-Zanussi-ZDSβ¦
@EarthOrgUK@mastodon.energyOn the Zanussi ZDS2010 freestanding slimline dishwasher: Review - Read all about how it worked for us and lasted longer than expected (with some TLC), but is sadly barely more efficient than the old model. - https://www.earth.org.uk/note-on-Zanussi-ZDSβ¦
@kexpmusicbot@mastodonapp.ukπΊπ¦ #NowPlaying on KEXP's #MiddayShow
TLC:
π΅ No Scrubs
#TLC
https://bdstf.bandcamp.com/track/tlc-no-scrubs-bdstf-remix
https://open.spotify.com/track/2R5M5yS36iLE32UD4CThlS
@thomasfuchs@hachyderm.ioWonder if the disk drive needs some TLC, got this on a different install disk than on the first try
@radioeinsmusicbot@mastodonapp.ukπΊπ¦ Auf radioeins lΓ€uft...
TLC:
π΅ No Scrubs
#NowPlaying #TLC
https://open.spotify.com/track/3NpsJc5SOINskuK3z08Q9C
@arXiv_csAR_bot@mastoxiv.pageNITRO: High-Performance 3D NAND Flash-Based In-Storage Computing with Enhanced Activation Dataflow
Sanghun Shin, Sangyeon Kim, Gisan Ji, Sungju Ryu
https://arxiv.org/abs/2608.11920 https://arxiv.org/pdf/2608.11920 https://arxiv.org/html/2608.11920
arXiv:2608.11920v1 Announce Type: new
Abstract: In-storage computing (ISC) is considered a next-generation memory architecture for its ability to relieve the data bottleneck between the host and the memory. While the required resources of large language models (LLMs) have increased significantly in recent years, the memory density has not scaled accordingly. Recently, several works have studied NAND flash-based processing-in-memory (NAND-PIM) schemes to exploit the high density of the memory. However, they do not address the dataflow/buffer for the intermediate values, so a simple method is to deal with the values in the slow flash memory array. To overcome such a limitation, we propose a high-performance NAND flash-based ISC architecture with enhanced activation buffering. Instead of using the very slow flash memory array for the intermediate values, our architecture buffers the values in a fast DRAM subsystem. This approach effectively handles the high-latency penalties when activations are programmed into slower TLC NAND flash. We also introduce a distributed dataflow approach for the NAND-PIM array. This approach maximizes computational parallelism by employing efficient intra-plane data mapping. The results show that our proposed architecture achieves significant performance improvements, reducing the inference latency by up to 85% compared to the baseline.
toXiv_bot_toot
@kexpmusicbot@mastodonapp.ukπΊπ¦ #NowPlaying on KEXP's #MorningShow
TLC:
π΅ Creep
#TLC
https://duala.bandcamp.com/track/tlc-creep-edit
https://open.spotify.com/track/1aWV3uY3SIEZVbmv45oFWS
@BBC6MusicBot@mastodonapp.uk @EarthOrgUK@mastodon.energyOn the Zanussi ZDS2010 freestanding slimline dishwasher: Review - Read all about how it worked for us and lasted longer than expected (with some TLC), but is sadly barely more efficient than the old model. - https://www.earth.org.uk/note-on-Zanussi-ZDSβ¦
@arXiv_csAR_bot@mastoxiv.pageA Full-Stack Characterization of High-Bandwidth Flash for KV-Centric LLM Serving
Zhuoran Li, Zhuohang Bian, Xin Huang, Yibo Zhao, Guangyu Sun, Youwei Zhuo
https://arxiv.org/abs/2608.11668 https://arxiv.org/pdf/2608.11668 https://arxiv.org/html/2608.11668
arXiv:2608.11668v1 Announce Type: new
Abstract: High-Bandwidth Flash (HBF) stacks NAND behind a wide, package-local interface, giving flash-scale capacity with far better read latency and bandwidth than an SSD. This makes it tempting to keep an SSD-style Mooncake KV-offloading stack and swap only the backing tier for HBF. We test that substitution with an extended TokenSim, four complete two-hour Qwen-Bailian production traces, five dense and mixture-of-experts models, and H100/B200 profiles. Serving gets worse, not better, and a cost-benefit model explains why. A faster far tier helps only when read I/O is the serving bottleneck, reads outweigh writes, and delivered bandwidth is sustainable. All three must hold together, and transient KV fails every one. The package trade that buys flash costs GPU near-tier capacity and bandwidth, so average end-to-end latency rises 2--5.5x and maximum SLO goodput falls 1.1--2.7x across H100 and B200. Serving is almost insensitive to HBF's own read/write latency, and base-die near-memory compute does not raise the flash tier's share of the critical path. The two-tier hierarchy keeps reuse in the near tier and hands HBF a write-heavy stream, so writes outnumber reads on every trace. A 3D-ICE model shows that stream drives the stack to its thermal limit well below peak bandwidth, and a TLC tier wears out sooner than a capacity-matched SSD pool. The faster device yields a slower system because the package gives up more than the medium returns. HBF is not the problem; using it as a faster SSD for transient KV is. It belongs in serving as a selective, reuse-aware, write-budgeted, and thermally coordinated tier, not as a drop-in SSD replacement.
toXiv_bot_toot
@BBC6MusicBot@mastodonapp.uk @thomasfuchs@hachyderm.ioThese speakers are pretty dirty, will need some TLC
@kexpmusicbot@mastodonapp.ukπΊπ¦ #NowPlaying on KEXP's #Early
Death Cab for Cutie:
π΅ Waterfalls
#DeathCabforCutie
https://deathcabforcutie.bandcamp.com/track/waterfalls-tlc-cover
https://open.spotify.com/track/6wONdYws5sr3roVodRB7G2
@BBC6MusicBot@mastodonapp.uk @BBC6MusicBot@mastodonapp.uk
