Tootfinder

AheadComputing, which develops a breakthrough RISC-V CPU architecture for AI, raised a $30M Seed2 led by Eclipse, Toyota, and Cambium, for $53M in total funding (Kyt Dotson/SiliconANGLE)
https://siliconangle.com/2026/01/21/aheadcomputing-lands-3…

AheadComputing lands $30M to build RISC-V processors for AI data centers - SiliconANGLE
AheadComputing lands $30M to build RISC-V processors for AI data centers - SiliconANGLE

There are many things I could do at #39C3, and I brought
- some of my SpacemiT and other RISC-V boards
- a #DECT dev board by @…
- two TP-Link 4G route…

Sin RAM, sin discos duros, sin procesadores AMD ni GPU Nvidia... Este va a ser el año de Linux en los RISC-V

Qualcomm kauft RISC-V-Spezialisten Ventana Micro
Qualcomm sieht „erhebliches Potenzial zur Erweiterung der Grenzen von CPU-Technologie“ mithilfe von RISC-V. Eine Übernahme soll helfen.
https://www.

Q&A with SiFive co-founder Krste Asanović, who was part of the original team that developed RISC-V, on creating a company that builds IP around RISC-V, and more (Dr. Ian Cutress/More Than Moore)
https://morethanmoore.substack.com/p/an-interview-with-dr-krste-asan…

An Interview with Dr. Krste Asanović
Putting the Drive into RISC-V

Number of misrepresented statements on Phoronix: 1
https://www.phoronix.com/news/RISC-V-Security-CPU-Not-So-Good
No. This is, first of all, not a matter of the ISA.
It is more of an implementation issue, for any ISA, FWIW.
See the citations!
Su…

Security Researchers Find Current RISC-V CPU Implementations Coming Up Short
While many open-source enthusiasts like to flaunt RISC-V as not having the security challenges as x86_64 CPUs have seen over the past several years with various speculative execution / side-channel attacks and arguing for the benefits of an open-source ISA in stronger security, in practice it's not so clear-cut

This is the year of Linux on the Document

Yuning Liang will speak on 'Solving Pre-silicon Kernel Upstream for RISC-V First Ever' as part of our Kernel & Low Level Systems track at SCaLE 23x. Full details: https://www.socallinuxexpo.org/scale/23x

GlobalFoundries agrees to acquire Synopsys' ARC processor IP business, which includes ARC-V (RISC-V) and ARC CPU IP, and integrate it into its MIPS business (Nitin Dahad/EE Times)
https://www.eetimes.com/globalfoundries-mips-to-buy-arc-ip-business-from-…

there should be a program called `unrv32c` that decompresses the RISC-V instructions from stdin to stdout

Yuning Liang will speak on 'Accelerating Open Automotive Innovation: Flutter on RISC-V' as part of our Embedded Linux track at SCaLE 23x. Full details: https://www.socallinuxexpo.org/scale/23x

The RISC-V dev room at #FOSDEM is pretty full!
Many interesting and fun topics are covered. :)
https://fosdem.org/2026/schedule/track/risc-v/

SiFive will integrate Nvidia's NVLink Fusion infrastructure with its RISC-V processor IP platforms, allowing SiFive silicon to communicate with Nvidia GPUs (Marco Chiappetta/Forbes)
https://www.forbes.com/sites/marcochiappet

SiFive To Integrate Nvidia NVLink Fusion For Next-Gen AI Data Center Chips
SiFive has announced a partnership with Nvidia to integrate Nvidia’s NVLink Fusion interconnect technology into its forthcoming silicon platforms.

Chinese chipmaker SpacemiT, whose RISC-V-based K1 chip is used in industrial systems, robotics, edge computing, and AI devices, raised an ~$86M Series B (Bloomberg)
https://www.bloomberg.com/news/articles/2026-01-15/chinese-chipm…

New embedded toolchain bits for Debian today for aarch64-none-elf, arm-none-eabi and riscv64-unknown-elf.
binutils-embedded builds version 2.45.90.20260125.
gcc-arm-none-eabi uses Arm GNU Toolchain version 15.2.rel1 (2025-12-17). For arm and aarch64.
gcc-riscv64-unknown-elf is based off GCC 15.2. For 32- and 64-bit Risc-V.
picolibc 1.8.11. Now the only C library.
libstdc -arm-none-eabi and libstdc -riscv64-unknown-elf.
They're all in NEW, but should …

Opening a pull request on Sipeed's NanoKVM repo implementing this critical BeOS system function on their RISC-V Linux platform

Kids on the bus, all playing video games walking to the back to find a seat... jeesh, teach them to read and write some Rust 🦀 or computer architecture and have them implement RISC-V cores or smth.

Moar RISC-V!
I'm here for the fun/horror stories, now on writing mask ROMs (aka boot ROMs), presented by Nick Kossifidis.

"Building a C compiler with a team of parallel Claudes"
#AI #LLM #slop #NoAI

Hi! I'm Koffietje! (Not very original, might change that later.)
Obviously, I'm a big fan of coffee! Generally black, over-steeped in a French press. But lately I've been messing around with the Moka pot.
I'm also big on Linux. My daily driver is Fedora, which seems to work incredibly well on my computers. I'm also curious about ARM & RISC-V, and have dipped my toes into BSD. Always trying to learn more, and currently I'm working on my Bash skills, tryi…