Tootfinder

from my link log —
RISC-V: they should have known better.
https://dmitry.gr/?r=06. Thoughts&proj=12. RV
saved 2026-08-14 https://…

RISC-V: They Should Have Known Better - Dmitry.GR
Dmitry.GR: I am often asked to explain my distaste for RISC-V. Here it is.

I'm calling it: 20 years before a viable RISC-V desktop-grade chip that is a peer of its contemporary AMD64/ARM competition

I just ran a quick @… test with @… in QEMU for RISC-V - stay tuned for more :D

Found an issue with Risc-V ILP32E ABI in GCC today and am looking for guidance.
ILP32E stack need only be aligned to 4-bytes, however types wider than 4 bytes are listed as having wider alignment requirements in current GCC source.
So, when you take the address of an 8-byte value on the stack which is not 8-byte aligned and try to use it with -fsanitize=undefined, you get a UB fault.
Question: Is this a bug in ubsan? Or should all type alignment restrictions be relaxed unde…

And another anniversary:
5 years ago, the ET-SOC-1 was unveiled. 🥳🥳
https://www.eetimes.com/esperanto-emerges-from-stealth-with-1000-core-risc-v-ai-accelerator/

ROLoad-PMP: Securing Sensitive Operations for Kernels and Bare-Metal Firmware
Wende Tan, Chenyang Li, Yangyu Chen, Yuan Li, Chao Zhang, Jianping Wu
https://arxiv.org/abs/2608.13287 https://arxiv.org/pdf/2608.13287 https://arxiv.org/html/2608.13287
arXiv:2608.13287v1 Announce Type: new
Abstract: A common way for attackers to compromise victim systems is hijacking sensitive operations (e.g., control-flow transfers) with attacker-controlled inputs. Existing solutions in general only protect parts of these targets and have high performance overheads, which are impractical and hard to deploy on systems with limited resources (e.g., IoT devices) or for low-level software like kernels and bare-metal firmware. In this paper, we present a lightweight hardware-software co-design solution ROLoad-PMP to protect sensitive operations from being hijacked for low-level software. First, we propose new instructions, which only load data from read-only memory regions with specific keys, to guarantee the integrity of pointees pointed by (potentially corrupted) data pointers. Then, we provide a program hardening mechanism to protect sensitive operations, by classifying and placing their operands into read-only memory with different keys at compile-time and loading them with ROLoad-PMP-family instructions at runtime. We have implemented an FPGA-based prototype of ROLoad-PMP based on RISC-V, and demonstrated an important defense application, i.e., forward-edge control-flow integrity. Results showed that ROLoad-PMP only costs few extra hardware resources (< 1.40%). Moreover, it enables many lightweight (e.g., with negligible overheads < 0.853%) defenses, and provides broader and stronger security guarantees than existing hardware solutions, e.g., ARM BTI and Intel CET.
toXiv_bot_toot

myawww what a cute RISC-V board :3
https://www.cnx-software.com/2026/09/08/yuzukineko-a-linux-capable-allwinner-f101-64-bit-risc-v-sbc-with-raspberry-pi-pico-form-factor/

High-Level Synthesis of Efficient Pipelines with Visibility Control
Jungin Rhee, Minseong Jang, Jaewoo Kim, Jeehoon Kang
https://arxiv.org/abs/2607.18765 https://arxiv.org/pdf/2607.18765 https://arxiv.org/html/2607.18765
arXiv:2607.18765v1 Announce Type: new
Abstract: High-level synthesis (HLS) raises the abstraction of hardware design from concurrent register-transfer level (RTL) programs to sequential programs. Among the forms of parallelism HLS exploits, pipelining demands fine-grained control over pipeline structure and hazard resolution to achieve competitive power, performance, and area (PPA). However, existing tools either lack such control or sacrifice sequential semantics to provide it.
We present an HLS tool that embeds fine-grained pipeline control in a sequential programming model, enabling rapid design-space exploration. The tool builds on visibility control, a novel programming abstraction that unifies hazard resolution strategies including stalling, bypassing, speculation, deferred commit, and register renaming. We evaluate on in-order RISC-V cores, histograms, and an AES accelerator. On RISC-V cores, we implement stall, bypass, speculation, and register renaming; on histograms, we implement scheduling strategies that previously required RTL or concurrent programming models. Compiled pipelines outperform HLS tools with sequential semantics and achieve PPA comparable to hand-written RTL.
toXiv_bot_toot

And another anniversary:
5 years ago, the ET-SOC-1 was unveiled. 🥳🥳
https://www.eetimes.com/esperanto-emerges-from-stealth-with-1000-core-risc-v-ai-accelerator/
https://docs.hpc.gwdg.de/services/ftp/esperanto/index.html