Tootfinder

VIA is now doing RISC-V.
A very obvious move, but it's good to hear those news.
https://www.viatech.com/en/ic-products/galilee-r2/

IntrinTrans: LLM-based Intrinsic Code Translator for RISC-V Vector
Liutong Han, Zhiyuan Tan, Hongbin Zhang, Pengcheng Wang, Chu Kang, Mingjie Xing, Yanjun Wu
https://arxiv.org/abs/2510.10119

IntrinTrans: LLM-based Intrinsic Code Translator for RISC-V Vector
The use of intrinsic functions to exploit hardware-specific capabilities is an important approach for optimizing library performance. Many mainstream libraries implement a large number of vectorized algorithms on Arm or x86 SIMD intrinsic functions. With the rapid expansion of the RISC-V hardware-software ecosystem, there is a growing demand for support of the RISC-V Vector (RVV) extension. Translating existing vectorized intrinsic code onto RVV intrinsics is a practical and effective approach.…

A Direct Memory Access Controller (DMAC) for Irregular Data Transfers on RISC-V Linux Systems
Thomas Benz, Axel Vanoni, Michael Rogenmoser, Luca Benini
https://arxiv.org/abs/2510.12277

A Direct Memory Access Controller (DMAC) for Irregular Data Transfers on RISC-V Linux Systems
With the ever-growing heterogeneity in computing systems, driven by modern machine learning applications, pressure is increasing on memory systems to handle arbitrary and more demanding transfers efficiently. Descriptor-based direct memory access controllers (DMACs) allow such transfers to be executed by decoupling memory transfers from processing units. Classical descriptor-based DMACs are inefficient when handling arbitrary transfers of small unit sizes. Excessive descriptor size and the seri…

Linus Torvalds calls Google engineer's RISC-V code "garbage" in Linux 6.17 dispute: The engineer took the criticism well.
🐧 https://www.techspot.com/news/109019-linus-torvalds-calls-google-engineer-risc-v-code.html

Efficient and Accurate Downfacing Visual Inertial Odometry
Jonas K\"uhne, Christian Vogt, Michele Magno, Luca Benini
https://arxiv.org/abs/2509.10021 https://

Efficient and Accurate Downfacing Visual Inertial Odometry
Visual Inertial Odometry (VIO) is a widely used computer vision method that determines an agent's movement through a camera and an IMU sensor. This paper presents an efficient and accurate VIO pipeline optimized for applications on micro- and nano-UAVs. The proposed design incorporates state-of-the-art feature detection and tracking methods (SuperPoint, PX4FLOW, ORB), all optimized and quantized for emerging RISC-V-based ultra-low-power parallel systems on chips (SoCs). Furthermore, by employin…

Systematic Assessment of Cache Timing Vulnerabilities on RISC-V Processors
C\'edrick Austa, Jan Tobias M\"uhlberg, Jean-Michel Dricot
https://arxiv.org/abs/2510.08272 h…

Systematic Assessment of Cache Timing Vulnerabilities on RISC-V Processors
While interest in the open RISC-V instruction set architecture is growing, tools to assess the security of concrete processor implementations are lacking. There are dedicated tools and benchmarks for common microarchitectural side-channel vulnerabilities for popular processor families such as Intel x86-64 or ARM, but not for RISC-V. In this paper we describe our efforts in porting an Intel x86-64 benchmark suite for cache-based timing vulnerabilities to RISC-V. We then use this benchmark to eva…

Co-designing a Programmable RISC-V Accelerator for MPC-based Energy and Thermal Management of Many-Core HPC Processors
Alessandro Ottaviano, Andrino Meli, Paul Scheffler, Giovanni Bambini, Robert Balas, Davide Rossi, Andrea Bartolini, Luca Benini
https://arxiv.org/abs/2510.09163

Co-designing a Programmable RISC-V Accelerator for MPC-based Energy and Thermal Management of Many-Core HPC Processors
Managing energy and thermal profiles is critical for many-core HPC processors with hundreds of application-class processing elements (PEs). Advanced model predictive control (MPC) delivers state-of-the-art performance but requires solving an online optimization problem over a thousand times per second (1 kHz control bandwidth), with computational and memory demands scaling with PE count. Traditional MPC approaches execute the controller on the PEs, but operating system overheads create jitter a…

Linus #Torvalds rantet mal wieder:
Der Code sei "Garbage" und "That thing makes the world actively a worse place to live". 😉
https://lore.kernel.org/lkml…

At the 2025 RISC-V Summit in China, Nvidia says CUDA will now be compatible with RISC-V's instruction set architecture, making RISC-V a viable x86 and Arm rival (Anton Shilov/Tom's Hardware)
https://www.

Nvidia's CUDA platform now supports RISC-V — support brings open source instruction set to AI platforms, joining x86 and Arm
Yet another alternative.

ARISE: Automating RISC-V Instruction Set Extension
Andreas Hager-Clukas, Philipp van Kempen, Stefan Wallentowitz
https://arxiv.org/abs/2508.07725 https://a…

ARISE: Automating RISC-V Instruction Set Extension
RISC-V is an extendable Instruction Set Architecture, growing in popularity for embedded systems. However, optimizing it to specific requirements, imposes a great deal of manual effort. To bridge the gap between software and ISA, the tool ARISE is presented. It automates the generation of RISC-V instructions based on assembly patterns, which are selected by an extendable set of metrics. These metrics implement the optimization goals of code size and instruction count reduction, both statically …

A 66-Gb/s/5.5-W RISC-V Many-Core Cluster for 5G Software-Defined Radio Uplinks
Marco Bertuletti, Yichao Zhang, Alessandro Vanelli-Coralli, Luca Benini
https://arxiv.org/abs/2508.06176

A 66-Gb/s/5.5-W RISC-V Many-Core Cluster for 5G+ Software-Defined Radio Uplinks
Following the scale-up of new radio (NR) complexity in 5G and beyond, the physical layer's computing load on base stations is increasing under a strictly constrained latency and power budget; base stations must process > 20-Gb/s uplink wireless data rate on the fly, in < 10 W. At the same time, the programmability and reconfigurability of base station components are the key requirements; it reduces the time and cost of new networks' deployment, it lowers the acceptance threshold for industry pl…

Ah yes, MIPS Technologies.
https://mips.com/products/hardware/
The famous designer of MIPS (microprocessor without interlocked pipeline stages) architecture processors.
Such a well named company /s

IP Processors - MIPS
Products Forging a New Path for the AI Compute Era Billions of Units Shipped MIPS Sub-Systems – More than a Core A foundation of compute DNA built over decades with billions of units shipped Bring Your Own Accelerators Flexible Integration Coherent Through Coherence Manager Fabric or Connect Direct to CPU RISC-V Core RISC-V Multi-threading Custom […]

from my link log —
RISC-V conditional moves.
https://www.corsix.org/content/riscv-conditional-moves
saved 2025-09-28 https://

TurboFuzz: FPGA Accelerated Hardware Fuzzing for Processor Agile Verification
Yang Zhong, Haoran Wu, Xueqi Li, Sa Wang, David Boland, Yungang Bao, Kan Shi
https://arxiv.org/abs/2509.10400

TurboFuzz: FPGA Accelerated Hardware Fuzzing for Processor Agile Verification
Verification is a critical process for ensuring the correctness of modern processors. The increasing complexity of processor designs and the emergence of new instruction set architectures (ISAs) like RISC-V have created demands for more agile and efficient verification methodologies, particularly regarding verification efficiency and faster coverage convergence. While simulation-based approaches now attempt to incorporate advanced software testing techniques such as fuzzing to improve coverage,…

Dissecting RISC-V Performance: Practical PMU Profiling and Hardware-Agnostic Roofline Analysis on Emerging Platforms
Alexander Batashev
https://arxiv.org/abs/2507.22451 https://…

Dissecting RISC-V Performance: Practical PMU Profiling and Hardware-Agnostic Roofline Analysis on Emerging Platforms
As RISC-V architectures proliferate across embedded and high-performance domains, developers face persistent challenges in performance optimization due to fragmented tooling, immature hardware features, and platform-specific defects. This paper delivers a pragmatic methodology for extracting actionable performance insights on RISC-V systems, even under constrained or unreliable hardware conditions. We present a workaround to circumvent hardware bugs in one of the popular RISC-V implementations,…

Synthesis of Sound and Precise Leakage Contracts for Open-Source RISC-V Processors
Zilong Wang, Gideon Mohr, Klaus von Gleissenthall, Jan Reineke, Marco Guarnieri
https://arxiv.org/abs/2509.06509

Synthesis of Sound and Precise Leakage Contracts for Open-Source RISC-V Processors
Leakage contracts have been proposed as a new security abstraction at the instruction set architecture level. Leakage contracts aim to capture the information that processors may leak via microarchitectural side channels. Recently, the first tools have emerged to verify whether a processor satisfies a given contract. However, coming up with a contract that is both sound and precise for a given processor is challenging, time-consuming, and error-prone, as it requires in-depth knowledge of the ti…

RV32I in ACL2
Carl Kwan (The University of Texas at Austin)
https://arxiv.org/abs/2507.19009 https://arxiv.org/pdf/2507.19009

RV32I in ACL2
We present a simple ACL2 simulator for the RISC-V 32-bit base instruction set architecture, written in the operational semantics style. Like many other ISA models, our RISC-V state object is a single-threaded object and we prove read-over-write, write-over-write, writing-the-read, and state well-formedness theorems. Unlike some other models, we separate the instruction decoding functions from their semantic counterparts. Accordingly, we verify encoding / decoding functions for each RV32I instru…

Programming RISC-V accelerators via Fortran
Nick Brown, Jake Davies, Felix LeClair
https://arxiv.org/abs/2510.02170 https://arxiv.org/pdf/2510.02170…

Programming RISC-V accelerators via Fortran
A range of RISC-V based accelerators are available and coming to market, and there is strong potential for these to be used for High Performance Computing (HPC) workloads. However, such accelerators tend to provide bespoke programming models and APIs that require codes to be rewritten. In scientific computing, where many of the simulation code are highly complex, extensive, and written in Fortran, this is not realistic. In this extended abstract we present an approach that enables driving such …

IzhiRISC-V -- a RISC-V-based Processor with Custom ISA Extension for Spiking Neuron Networks Processing with Izhikevich Neurons
Wiktor J. Szczerek, Artur Podobas
https://arxiv.org/abs/2508.12846

IzhiRISC-V -- a RISC-V-based Processor with Custom ISA Extension for Spiking Neuron Networks Processing with Izhikevich Neurons
Spiking Neural Network processing promises to provide high energy efficiency due to the sparsity of the spiking events. However, when realized on general-purpose hardware -- such as a RISC-V processor -- this promise can be undermined and overshadowed by the inefficient code, stemming from repeated usage of basic instructions for updating all the neurons in the network. One of the possible solutions to this issue is the introduction of a custom ISA extension with neuromorphic instructions for s…

Doing some more RISC-V again... 👀
We got:
- Sipeed Lichee RV Dock Pro (Allwinner D1)
- Milk-V Mars CM (StarFive JH7110)
- OrangePi RV2 (Ky X1, really SpacemiT K1)

Replaced article(s) found for cs.AR. https://arxiv.org/list/cs.AR/new
[1/1]:
- ControlPULPlet: A Flexible Real-time Multi-core RISC-V Controller for 2.5D Systems-in-package
Alessandro Ottaviano, Robert Balas, Tim Fischer, Thomas Benz, Andrea Bartolini, Luca Benini

Evolution of Kernels: Automated RISC-V Kernel Optimization with Large Language Models
Siyuan Chen, Zhichao Lu, Qingfu Zhang
https://arxiv.org/abs/2509.14265 https://

Evolution of Kernels: Automated RISC-V Kernel Optimization with Large Language Models
Automated kernel design is critical for overcoming software ecosystem barriers in emerging hardware platforms like RISC-V. While large language models (LLMs) have shown promise for automated kernel optimization, demonstrating success in CUDA domains with comprehensive technical documents and mature codebases, their effectiveness remains unproven for reference-scarce domains like RISC-V. We present Evolution of Kernels (EoK), a novel LLM-based evolutionary program search framework that automates…

Bridging Simulation and Silicon: A Study of RISC-V Hardware and FireSim Simulation
Atanu Barai, Kamalavasan Kamalakkannan, Patrick Diehl, Maxim Moraru, Jered Dominguez-Trujillo, Howard Pritchard, Nandakishore Santhi, Farzad Fatollahi-Fard, Galen Shipman
https://arxiv.org/abs/2509.18472

Upcoming next week:
3rd European RISC-V #Firmware and #Embedded #Rust #Workshop by EDA Centrum at V…

Great find of the day:
RISC-V actually defines #platforms now! 🥳
https://github.com/riscv/riscv-profiles/…

riscv-profiles/src/profiles.adoc at 6aecbe43af5289676a87eee085380b75b8aa597e · riscv/riscv-profiles
RISC-V Architecture Profiles. Contribute to riscv/riscv-profiles development by creating an account on GitHub.

Accelerating Gravitational $N$-Body Simulations Using the RISC-V-Based Tenstorrent Wormhole
Jenny Lynn Almerol, Elisabetta Boella, Mario Spera, Daniele Gregori
https://arxiv.org/abs/2509.19294

MARVEL: An End-to-End Framework for Generating Model-Class Aware Custom RISC-V Extensions for Lightweight AI
Ajay Kumar M, Cian O'Mahoney, Pedro Kreutz Werle, Shreejith Shanker, Dimitrios S. Nikolopoulos, Bo Ji, Hans Vandierendonck, Deepu John
https://arxiv.org/abs/2508.01800

MARVEL: An End-to-End Framework for Generating Model-Class Aware Custom RISC-V Extensions for Lightweight AI
Deploying deep neural networks (DNNs) on resource-constrained IoT devices remains a challenging problem, often requiring hardware modifications tailored to individual AI models. Existing accelerator-generation tools, such as AMD's FINN, do not adequately address extreme resource limitations faced by IoT endpoints operating in bare-metal environments without an operating system (OS). To overcome these constraints, we propose MARVEL-an automated, end-to-end framework that generates custom RISC-V …

Is RISC-V ready for High Performance Computing? An evaluation of the Sophon SG2044
Nick Brown
https://arxiv.org/abs/2508.13840 https://arxiv.org/pdf/2508.1…

Is RISC-V ready for High Performance Computing? An evaluation of the Sophon SG2044
The pace of RISC-V adoption continues to grow rapidly, yet for the successes enjoyed in areas such as embedded computing, RISC-V is yet to gain ubiquity in High Performance Computing (HPC). The Sophon SG2044 is SOPHGO's next generation 64-core high performance CPU that has been designed for workstation and server grade workloads. Building upon the SG2042, subsystems that were a bottleneck in the previous generation have been upgraded. In this paper we undertake the first performance study of …

Pedagogically Motivated and Composable Open-Source RISC-V Processors for Computer Science Education
Ian McDougall, Harish Batchu, Michael Davies, Karthikeyan Sankaralingam
https://arxiv.org/abs/2509.20514

Pedagogically Motivated and Composable Open-Source RISC-V Processors for Computer Science Education
While most instruction set architectures (ISAs) are only available to use through the purchase of a restrictive commercial license, the RISC-V ISA presents a free and open-source alternative. Due to this availability, many free and open-source implementations have been developed and can be accessed on platforms such as GitHub. If an open source, easy-to-use, and robust RISC-V implementation could be obtained, it could be easily adapted for pedagogical and amateur use. In this work we accomplish…

If it still fits on a billboard, it's not a RISC-V ISA string. 😁

Accelerating GenAI Workloads by Enabling RISC-V Microkernel Support in IREE
Adeel Ahmad, Ahmad Tameem Kamal, Nouman Amir, Bilal Zafar, Saad Bin Nasir
https://arxiv.org/abs/2508.14899

Accelerating GenAI Workloads by Enabling RISC-V Microkernel Support in IREE
This project enables RISC-V microkernel support in IREE, an MLIR-based machine learning compiler and runtime. The approach begins by enabling the lowering of MLIR linalg dialect contraction ops to linalg.mmt4d op for the RISC-V64 target within the IREE pass pipeline, followed by the development of optimized microkernels for RISC-V. The performance gains are compared with upstream IREE and Llama.cpp for the Llama-3.2-1B-Instruct model.

Bare-Metal RISC-V NVDLA SoC for Efficient Deep Learning Inference
Vineet Kumar (School of Electrical,Electronic Engineering, University College Dublin, Dublin, Ireland, Department of Electronic,Electrical Engineering, Trinity College Dublin, Dublin, Ireland), Ajay Kumar M (School of Electrical,Electronic Engineering, University College Dublin, Dublin, Ireland, Department of Electronic,Electrical Engineering, Trinity College Dublin, Dublin, Ireland), Yike Li (School of Electrical,Elec…

Bare-Metal RISC-V + NVDLA SoC for Efficient Deep Learning Inference
This paper presents a novel System-on-Chip (SoC) architecture for accelerating complex deep learning models for edge computing applications through a combination of hardware and software optimisations. The hardware architecture tightly couples the open-source NVIDIA Deep Learning Accelerator (NVDLA) to a 32-bit, 4-stage pipelined RISC-V core from Codasip called uRISC_V. To offload the model acceleration in software, our toolflow generates bare-metal application code (in assembly), overcoming co…

Flexible Vector Integration in Embedded RISC-V SoCs for End to End CNN Inference Acceleration
Dmitri Lyalikov
https://arxiv.org/abs/2507.17771 https://arxi…

Flexible Vector Integration in Embedded RISC-V SoCs for End to End CNN Inference Acceleration
The emergence of heterogeneity and domain-specific architectures targeting deep learning inference show great potential for enabling the deployment of modern CNNs on resource-constrained embedded platforms. A significant development is the diversification of custom hardware solely targeting the most expensive parts of CNNs. DLAs (deep learning accelerators) and NPUs (neural processing units), among others, can overcome the approaching limits of traditional silicon scaling and provide a solution…

Chiplet-Based RISC-V SoC with Modular AI Acceleration
P. Ramkumar, S. S. Bharadwaj
https://arxiv.org/abs/2509.18355 https://arxiv.org/pdf/2509.18355…

Efficient Column-Wise N:M Pruning on RISC-V CPU
Chi-Wei Chu, Ding-Yong Hong, Jan-Jan Wu
https://arxiv.org/abs/2507.17301 https://arxiv.org/pdf/2507.17301…

Efficient Column-Wise N:M Pruning on RISC-V CPU
In deep learning frameworks, weight pruning is a widely used technique for improving computational efficiency by reducing the size of large models. This is especially critical for convolutional operators, which often act as performance bottlenecks in convolutional neural networks (CNNs). However, the effectiveness of pruning heavily depends on how it is implemented, as different methods can significantly impact both computational performance and memory footprint. In this work, we propose a colu…

X-HEEP: An Open-Source, Configurable and Extendible RISC-V Platform for TinyAI Applications
Simone Machetti, Pasquale Davide Schiavone, Giovanni Ansaloni, Miguel Pe\'on-Quir\'os, David Atienza
https://arxiv.org/abs/2508.16959

X-HEEP: An Open-Source, Configurable and Extendible RISC-V Platform for TinyAI Applications
In this work, we present X-HEEP, an open-source, configurable, and extendible RISC-V platform for ultra-low-power edge applications (TinyAI). X-HEEP features the eXtendible Accelerator InterFace (XAIF), which enables seamless integration of accelerators with varying requirements along with an extensive internal configuration of cores, memory, bus, and peripherals. Moreover, it supports various development flows, including FPGA prototyping, ASIC implementation, and mixed SystemC-RTL modeling, en…

Runtime Energy Monitoring for RISC-V Soft-Cores
Alberto Scionti, Paolo Savio, Francesco Lubrano, Olivier Terzo, Marco Ferretti, Florin Apopei, Juri Bellucci, Ennio Spano, Luca Carriere
https://arxiv.org/abs/2509.26065

Runtime Energy Monitoring for RISC-V Soft-Cores
Energy efficiency is one of the major concern in designing advanced computing infrastructures. From single nodes to large-scale systems (data centers), monitoring the energy consumption of the computing system when applications run is a critical task. Designers and application developers often rely on software tools and detailed architectural models to extract meaningful information and determine the system energy consumption. However, when a design space exploration is required, designers may …

Next week, I will be at Kernel Recipes and see that I grab someone to talk about some kernel debugging issues.
At the weekend, I will then be at LinuxDay.at, where I am going to present on the status of mainline Linux for RISC-V.
I am super excited already. \o/

Replaced article(s) found for cs.AR. https://arxiv.org/list/cs.AR/new
[1/1]:
- Unlimited Vector Processing for Wireless Baseband Based on RISC-V Extension
Limin Jiang, Yi Shi, Yihao Shen, Shan Cao, Zhiyuan Jiang, Sheng Zhou

Microarchitecture Design and Benchmarking of Custom SHA-3 Instruction for RISC-V
Alperen Bolat, Sakir Sezer, Kieran McLaughlin, Henry Hui
https://arxiv.org/abs/2508.20653 https:…

Microarchitecture Design and Benchmarking of Custom SHA-3 Instruction for RISC-V
Integrating cryptographic accelerators into modern CPU architectures presents unique microarchitectural challenges, particularly when extending instruction sets with complex and multistage operations. Hardware-assisted cryptographic instructions, such as Intel's AES-NI and ARM's custom instructions for encryption workloads, have demonstrated substantial performance improvements. However, efficient SHA-3 acceleration remains an open problem due to its distinct permutation-based structure and mem…

Support Vector Machines Classification on Bendable RISC-V
Polykarpos Vergos, Theofanis Vergos, Florentia Afentaki, Konstantinos Balaskas, Georgios Zervakis
https://arxiv.org/abs/2508.19656

Support Vector Machines Classification on Bendable RISC-V
Flexible Electronics (FE) technology offers uniquecharacteristics in electronic manufacturing, providing ultra-low-cost, lightweight, and environmentally-friendly alternatives totraditional rigid electronics. These characteristics enable a rangeof applications that were previously constrained by the costand rigidity of conventional silicon technology. Machine learning (ML) is essential for enabling autonomous, real-time intelligenceon devices with smart sensing capabilities in everyday objects.…

Flexible Vector Integration in Embedded RISC-V SoCs for End to End CNN Inference Acceleration
Dmitri Lyalikov
https://arxiv.org/abs/2507.17771 https://arxi…

Automatic Microarchitecture-Aware Custom Instruction Design for RISC-V Processors
Evgenii Rezunov, Niko Zurstra{\ss}en, Lennart M. Reimann, Rainer Leupers
https://arxiv.org/abs/2509.15782

Automatic Microarchitecture-Aware Custom Instruction Design for RISC-V Processors
An Application-Specific Instruction Set Processor(ASIP) is a specialized microprocessor that provides a trade-off between the programmability of a General Purpose Processor (GPP) and the performance and energy-efficiency of dedicated hardware accelerators. ASIPs are often derived from off-the-shelf GPPs extended by custom instructions tailored towards a specific software workload. One of the most important challenges of designing an ASIP is to find said custom instructions that help to increase…

Modular SAIL: dream or reality?
Petr Kourzanov, Anmol
https://arxiv.org/abs/2507.12471 https://arxiv.org/pdf/2507.12471

Modular SAIL: dream or reality?
In order to truly benefit from RISC-V ISA modularity, the community has to address the issue of compositionality, going beyond modules at the specification level covering larger subsets of the RISC-V development flow including emulation, simulation and verification. In this paper we introduce modular SAIL, an experiment to inject compositionality into the SAIL-RISCV golden model. We show that it is, in principle, not difficult to adapt the SAIL-RISCV flow (and ideally the SAIL compiler itself) …

Crosslisted article(s) found for cs.AR. https://arxiv.org/list/cs.AR/new
[1/1]:
- Decentor-V: Lightweight ML Training on Low-Power RISC-V Edge Devices
Marcelo Ribeiro, Diogo Costa, Gon\c{c}alo Moreira, Sandro Pinto, Tiago Gomes

Crosslisted article(s) found for cs.AR. https://arxiv.org/list/cs.AR/new
[1/1]:
- MaRVIn: A Cross-Layer Mixed-Precision RISC-V Framework for DNN Inference, from ISA Extension to H...
Giorgos Armeniakos, Alexis Maras, Sotirios Xydis, Dimitrios Soudris