Tootfinder

Parallel FFTW on RISC-V: A Comparative Study including OpenMP, MPI, and HPX
Alexander Strack, Christopher Taylor, Dirk Pfl\"uger
https://arxiv.org/abs/2506.08653

Parallel FFTW on RISC-V: A Comparative Study including OpenMP, MPI, and HPX
Rapid advancements in RISC-V hardware development shift the focus from low-level optimizations to higher-level parallelization. Recent RISC-V processors, such as the SOPHON SG2042, have 64 cores. RISC-V processors with core counts comparable to the SG2042, make efficient parallelization as crucial for RISC-V as the more established processors such as x86-64. In this work, we evaluate the parallel scaling of the widely used FFTW library on RISC-V for MPI and OpenMP. We compare it to a 64-core AM…

Towards Zero-Stall Matrix Multiplication on Energy-Efficient RISC-V Clusters for Machine Learning Acceleration
Luca Colagrande, Lorenzo Leone, Maximilian Coco, Andrei Deaconeasa, Luca Benini
https://arxiv.org/abs/2506.10921

Towards Zero-Stall Matrix Multiplication on Energy-Efficient RISC-V Clusters for Machine Learning Acceleration
The growing computational demands of machine learning (ML) workloads have driven the design of ML accelerators aiming at an optimal tradeoff between efficiency and flexibility. A widely explored architecture for flexible ML accelerators is based on clusters of lightweight instruction processors sharing multi-banked L1 memory, augmented with specialized instruction extensions for key ML-related computations, such as matrix multiplication (matmul). However, instruction extensions should be couple…

Design and Implementation of a RISC-V SoC with Custom DSP Accelerators for Edge Computing
Priyanshu Yadav
https://arxiv.org/abs/2506.06693 https://

Design and Implementation of a RISC-V SoC with Custom DSP Accelerators for Edge Computing
This paper presents a comprehensive analysis of the RISC-V instruction set architecture, focusing on its modular design, implementation challenges, and performance characteristics. We examine the RV32I base instruction set with extensions for multiplication (M) and atomic operations (A). Through cycle-accurate simulation of a pipelined implementation, we evaluate performance metrics including CPI (cycles per instruction) and power efficiency. Our results demonstrate RISC-V's advantages in embed…

FREESS: An Educational Simulator of a RISC-V-Inspired Superscalar Processor Based on Tomasulo's Algorithm
Roberto Giorgi
https://arxiv.org/abs/2506.07665

FREESS: An Educational Simulator of a RISC-V-Inspired Superscalar Processor Based on Tomasulo's Algorithm
FREESS is a free, interactive simulator that illustrates instruction-level parallelism in a RISC-V-inspired superscalar processor. Based on an extended version of Tomasulo's algorithm, FREESS is intended as a hands-on educational tool for Advanced Computer Architecture courses. It enables students to explore dynamic, out-of-order instruction execution, emphasizing how instructions are issued as soon as their operands become available. The simulator models key microarchitectural components, in…

Ich habe eine AI gefragt, welchen Hostnamen ich denn einem RISC-V-Laptop geben könnte. Und naja … das Laptop heißt jetzt RiscVader. 🤡

Enabling Syscall Intercept for RISC-V
Petar Andri\'c, Aaron Call, Ramon Nou
https://arxiv.org/abs/2505.10217 https://arxiv.org/pd…

Enabling Syscall Intercept for RISC-V
The European Union technological sovereignty strategy centers around the RISC-V Instruction Set Architecture, with the European Processor Initiative leading efforts to build production-ready processors. Focusing on realizing a functional RISC-V ecosystem, the BZL initiative (www.bzl.es) is making an effort to create a software stack along with the hardware. In this work, we detail the efforts made in porting a widely used syscall interception library, mainly used on AdHocFS (i.e., DAOS, GekkoFS…

Welche Ideen habt ihr, einen Zoo von „Spielzeuglaptops“ ordentlich aufzubewahren? Momentan liegen die Geräte hier erratisch mal auf dem Schreibtisch, mal im Regal. Geht um derzeit sechs Geräte, verschiedene CPU-Architekturen, verschiedene Betriebssysteme, Größen zwischen 9“ (so ein Winzig-Risc-V) und 14“. Aufbewahrung sollte incl. zugehöriger Netzteile sein und Platz für noch 2-3 weitere Geräte haben. Momentan bin ich bei „hochkant in einem Hartschalenkoffer mit so Schaumstoffwürfelchen“.

As part of the #IWP9 #hackathon, we were debugging the bringup of the RISC-V port of 9front to QEMU yesterday. It was really painful, compared to my experiences with other kernels like Linux and the ease of Rust and its built-in print format capabilities. We were finally able to use uartputs with a s…

Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution
Zexin Fu, Riccardo Tedeschi, Gianmarco Ottavi, Nils Wistoff, C\'esar Fuguet, Davide Rossi, Luca Benini
https://arxiv.org/abs/2505.24363

Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution
Open-source RISC-V cores are increasingly demanded in domains like automotive and space, where achieving high instructions per cycle (IPC) through superscalar and out-of-order (OoO) execution is crucial. However, high-performance open-source RISC-V cores face adoption challenges: some (e.g. BOOM, Xiangshan) are developed in Chisel with limited support from industrial electronic design automation (EDA) tools. Others, like the XuanTie C910 core, use proprietary interfaces and protocols, including…

This https://arxiv.org/abs/2505.07112 has been replaced.
initial toot: https://mastoxiv.page/@arXiv_csAR_…

Efficient Implementation of RISC-V Vector Permutation Instructions
RISC-V CPUs leverage the RVV (RISC-V Vector) extension to accelerate data-parallel workloads. In addition to arithmetic operations, RVV includes powerful permutation instructions that enable flexible element rearrangement within vector registers --critical for optimizing performance in tasks such as matrix operations and cryptographic computations. However, the diverse control mechanisms of these instructions complicate their execution within a unified datapath while maintaining the fixed-laten…

This https://arxiv.org/abs/2505.08421 has been replaced.
initial toot: https://mastoxiv.page/@arXiv_csAR_…

e-GPU: An Open-Source and Configurable RISC-V Graphic Processing Unit for TinyAI Applications
Graphics processing units (GPUs) excel at parallel processing, but remain largely unexplored in ultra-low-power edge devices (TinyAI) due to their power and area limitations, as well as the lack of suitable programming frameworks. To address these challenges, this work introduces embedded GPU (e-GPU), an open-source and configurable RISC-V GPU platform designed for TinyAI devices. Its extensive configurability enables area and power optimization, while a dedicated Tiny-OpenCL implementation pro…

Enable Lightweight and Precision-Scalable Posit/IEEE-754 Arithmetic in RISC-V Cores for Transprecision Computing
Qiong Li, Chao Fang, Longwei Huang, Jun Lin, Zhongfeng Wang
https://arxiv.org/abs/2505.19096

Enable Lightweight and Precision-Scalable Posit/IEEE-754 Arithmetic in RISC-V Cores for Transprecision Computing
While posit format offers superior dynamic range and accuracy for transprecision computing, its adoption in RISC-V processors is hindered by the lack of a unified solution for lightweight, precision-scalable, and IEEE-754 arithmetic compatible hardware implementation. To address these challenges, we enhance RISC-V processors by 1) integrating dedicated posit codecs into the original FPU for lightweight implementation, 2) incorporating multi/mixed-precision support with dynamic exponent size for…