Tootfinder

from my link log —
Removing the AUICGP instruction from CHERIoT RISC V.
https://cheriot.org/isa/toolchain/2026/03/23/removing-auicgp.html
saved 2026-04-25

Erste SSD: Samsung wechselt von ARM auf RISC-V
Samsung kündigt eine erste SSD an, in deren Controller RISC-V-Kerne sitzen. Der Hersteller verspricht eine höhere Effizienz.
https://www.heise.de/ne…

Report: Alibaba's DAMO Academy unveils XuanTie C950, a 5nm server chip with 3.2 GHz clock, and claims it to be "the highest performing RISC-V CPU in the world" (Reuters)
https://www.reuters.com/world/asia-pacific

Sin RAM, sin discos duros, sin procesadores AMD ni GPU Nvidia... Este va a ser el año de Linux en los RISC-V

Number of misrepresented statements on Phoronix: 1
https://www.phoronix.com/news/RISC-V-Security-CPU-Not-So-Good
No. This is, first of all, not a matter of the ISA.
It is more of an implementation issue, for any ISA, FWIW.
See the citations!
Su…

Security Researchers Find Current RISC-V CPU Implementations Coming Up Short
While many open-source enthusiasts like to flaunt RISC-V as not having the security challenges as x86_64 CPUs have seen over the past several years with various speculative execution / side-channel attacks and arguing for the benefits of an open-source ISA in stronger security, in practice it's not so clear-cut

from my link log —
Running modern code on a 1960s UNIVAC computer via a RISC V emulator.
https://farlow.dev/2026/04/17/running-a-minecraft-server-and-more-on-a-1960s-univac-computer
saved 2026-04-18

"MIPS RISC-V Processors" kinda reads funny.
Anyway, MIPS is now a RISC-V company.
First patches appeared on the U-Boot mailing list.
https://mips.com/products/hardware/p8700/

P8700 CPU, Redefining High-Performance Compute Multi-Cores
Explore the capabilities of the MIPS P8700, bring your own accelerators and achieve high performance, low power and reduced latency.

Yuning Liang will speak on 'Accelerating Open Automotive Innovation: Flutter on RISC-V' as part of our Embedded Linux track at SCaLE 23x. Full details: https://www.socallinuxexpo.org/scale/23x

RISC-V chip designer SiFive raised a $400M Series G led by Atreides at a $3.65B valuation; CEO Patrick Little says it is the final funding round before an IPO (Stephen Nellis/Reuters)
https://www.reuters.com/business/sifive-ra

The RISC-V dev room at #FOSDEM is pretty full!
Many interesting and fun topics are covered. :)
https://fosdem.org/2026/schedule/track/risc-v/

Yuning Liang will speak on 'Solving Pre-silicon Kernel Upstream for RISC-V First Ever' as part of our Kernel & Low Level Systems track at SCaLE 23x. Full details: https://www.socallinuxexpo.org/scale/23x

from my link log —
Mark’s magic multiply: Xh3sfx RISC V extension for accelerated software floating point.
https://wren.wtf/shower-thoughts/marks-magic-multiply/
saved 2026-04-12

AI slop proudly pretends:
"Symmetric Mmplsstpecying (SMP)"
(almost looks like a RISC-V extension)
https://www.serverion.com/uncategorized/preempt-rt-explained-real-time-kernel-features/
... like wtf, noone even both…

from my link log —
Optimising a pipelined RISC-V core: from naive pipeline to near-superscalar performance.
https://mummanajagadeesh.github.io/blogs/optm-riscv-core/
saved 2026-04-07

A few years ago, I gave a talk at RISC-V on #documentation, with some hints on automatically generating it. They are doing this now in practice for #Baochip:

"Building a C compiler with a team of parallel Claudes"
#AI #LLM #slop #NoAI

Moar RISC-V!
I'm here for the fun/horror stories, now on writing mask ROMs (aka boot ROMs), presented by Nick Kossifidis.

I could imagine starting a RISC-V chip design company called NeoV, but I feel like it could lead to misunderstandings.