Tootfinder

Qualcomm kauft RISC-V-Spezialisten Ventana Micro
Qualcomm sieht „erhebliches Potenzial zur Erweiterung der Grenzen von CPU-Technologie“ mithilfe von RISC-V. Eine Übernahme soll helfen.
https://www.

IntrinTrans: LLM-based Intrinsic Code Translator for RISC-V Vector
Liutong Han, Zhiyuan Tan, Hongbin Zhang, Pengcheng Wang, Chu Kang, Mingjie Xing, Yanjun Wu
https://arxiv.org/abs/2510.10119

IntrinTrans: LLM-based Intrinsic Code Translator for RISC-V Vector
The use of intrinsic functions to exploit hardware-specific capabilities is an important approach for optimizing library performance. Many mainstream libraries implement a large number of vectorized algorithms on Arm or x86 SIMD intrinsic functions. With the rapid expansion of the RISC-V hardware-software ecosystem, there is a growing demand for support of the RISC-V Vector (RVV) extension. Translating existing vectorized intrinsic code onto RVV intrinsics is a practical and effective approach.…

A Direct Memory Access Controller (DMAC) for Irregular Data Transfers on RISC-V Linux Systems
Thomas Benz, Axel Vanoni, Michael Rogenmoser, Luca Benini
https://arxiv.org/abs/2510.12277

A Direct Memory Access Controller (DMAC) for Irregular Data Transfers on RISC-V Linux Systems
With the ever-growing heterogeneity in computing systems, driven by modern machine learning applications, pressure is increasing on memory systems to handle arbitrary and more demanding transfers efficiently. Descriptor-based direct memory access controllers (DMACs) allow such transfers to be executed by decoupling memory transfers from processing units. Classical descriptor-based DMACs are inefficient when handling arbitrary transfers of small unit sizes. Excessive descriptor size and the seri…

Systematic Assessment of Cache Timing Vulnerabilities on RISC-V Processors
C\'edrick Austa, Jan Tobias M\"uhlberg, Jean-Michel Dricot
https://arxiv.org/abs/2510.08272 h…

Systematic Assessment of Cache Timing Vulnerabilities on RISC-V Processors
While interest in the open RISC-V instruction set architecture is growing, tools to assess the security of concrete processor implementations are lacking. There are dedicated tools and benchmarks for common microarchitectural side-channel vulnerabilities for popular processor families such as Intel x86-64 or ARM, but not for RISC-V. In this paper we describe our efforts in porting an Intel x86-64 benchmark suite for cache-based timing vulnerabilities to RISC-V. We then use this benchmark to eva…

Co-designing a Programmable RISC-V Accelerator for MPC-based Energy and Thermal Management of Many-Core HPC Processors
Alessandro Ottaviano, Andrino Meli, Paul Scheffler, Giovanni Bambini, Robert Balas, Davide Rossi, Andrea Bartolini, Luca Benini
https://arxiv.org/abs/2510.09163

Co-designing a Programmable RISC-V Accelerator for MPC-based Energy and Thermal Management of Many-Core HPC Processors
Managing energy and thermal profiles is critical for many-core HPC processors with hundreds of application-class processing elements (PEs). Advanced model predictive control (MPC) delivers state-of-the-art performance but requires solving an online optimization problem over a thousand times per second (1 kHz control bandwidth), with computational and memory demands scaling with PE count. Traditional MPC approaches execute the controller on the PEs, but operating system overheads create jitter a…

Kids on the bus, all playing video games walking to the back to find a seat... jeesh, teach them to read and write some Rust 🦀 or computer architecture and have them implement RISC-V cores or smth.

For some unspecific reason, RISC-V devices are somewhat piling up here. 🤷 #riscv #sbc

from my link log —
RISC-V conditional moves.
https://www.corsix.org/content/riscv-conditional-moves
saved 2025-09-28 https://

Doing some more RISC-V again... 👀
We got:
- Sipeed Lichee RV Dock Pro (Allwinner D1)
- Milk-V Mars CM (StarFive JH7110)
- OrangePi RV2 (Ky X1, really SpacemiT K1)

Programming RISC-V accelerators via Fortran
Nick Brown, Jake Davies, Felix LeClair
https://arxiv.org/abs/2510.02170 https://arxiv.org/pdf/2510.02170…

Programming RISC-V accelerators via Fortran
A range of RISC-V based accelerators are available and coming to market, and there is strong potential for these to be used for High Performance Computing (HPC) workloads. However, such accelerators tend to provide bespoke programming models and APIs that require codes to be rewritten. In scientific computing, where many of the simulation code are highly complex, extensive, and written in Fortran, this is not realistic. In this extended abstract we present an approach that enables driving such …

»AntCalc is a wrist-worn programmable calculator with scientific functions.«
The RPN calculator runs on a RISC-V processor, schematics and PCB layout is available at Github: https://www.breatharian.eu/hw/ch32libsdk/index_en.html#antcalc

Pedagogically Motivated and Composable Open-Source RISC-V Processors for Computer Science Education
Ian McDougall, Harish Batchu, Michael Davies, Karthikeyan Sankaralingam
https://arxiv.org/abs/2509.20514

Pedagogically Motivated and Composable Open-Source RISC-V Processors for Computer Science Education
While most instruction set architectures (ISAs) are only available to use through the purchase of a restrictive commercial license, the RISC-V ISA presents a free and open-source alternative. Due to this availability, many free and open-source implementations have been developed and can be accessed on platforms such as GitHub. If an open source, easy-to-use, and robust RISC-V implementation could be obtained, it could be easily adapted for pedagogical and amateur use. In this work we accomplish…

Evolution of Kernels: Automated RISC-V Kernel Optimization with Large Language Models
Siyuan Chen, Zhichao Lu, Qingfu Zhang
https://arxiv.org/abs/2509.14265 https://

Evolution of Kernels: Automated RISC-V Kernel Optimization with Large Language Models
Automated kernel design is critical for overcoming software ecosystem barriers in emerging hardware platforms like RISC-V. While large language models (LLMs) have shown promise for automated kernel optimization, demonstrating success in CUDA domains with comprehensive technical documents and mature codebases, their effectiveness remains unproven for reference-scarce domains like RISC-V. We present Evolution of Kernels (EoK), a novel LLM-based evolutionary program search framework that automates…

Bridging Simulation and Silicon: A Study of RISC-V Hardware and FireSim Simulation
Atanu Barai, Kamalavasan Kamalakkannan, Patrick Diehl, Maxim Moraru, Jered Dominguez-Trujillo, Howard Pritchard, Nandakishore Santhi, Farzad Fatollahi-Fard, Galen Shipman
https://arxiv.org/abs/2509.18472

Opening a pull request on Sipeed's NanoKVM repo implementing this critical BeOS system function on their RISC-V Linux platform

Accelerating Gravitational $N$-Body Simulations Using the RISC-V-Based Tenstorrent Wormhole
Jenny Lynn Almerol, Elisabetta Boella, Mario Spera, Daniele Gregori
https://arxiv.org/abs/2509.19294

Chiplet-Based RISC-V SoC with Modular AI Acceleration
P. Ramkumar, S. S. Bharadwaj
https://arxiv.org/abs/2509.18355 https://arxiv.org/pdf/2509.18355…

If it still fits on a billboard, it's not a RISC-V ISA string. 😁

Runtime Energy Monitoring for RISC-V Soft-Cores
Alberto Scionti, Paolo Savio, Francesco Lubrano, Olivier Terzo, Marco Ferretti, Florin Apopei, Juri Bellucci, Ennio Spano, Luca Carriere
https://arxiv.org/abs/2509.26065

Runtime Energy Monitoring for RISC-V Soft-Cores
Energy efficiency is one of the major concern in designing advanced computing infrastructures. From single nodes to large-scale systems (data centers), monitoring the energy consumption of the computing system when applications run is a critical task. Designers and application developers often rely on software tools and detailed architectural models to extract meaningful information and determine the system energy consumption. However, when a design space exploration is required, designers may …

»We have Doom running on the system in the demo room. Of course if Doom doesn't run on it, it is not real.« – Heard in a product introduction of some new Tenstorrent RISC-V silicon. #riscv #tenstorrent

Next week, I will be at Kernel Recipes and see that I grab someone to talk about some kernel debugging issues.
At the weekend, I will then be at LinuxDay.at, where I am going to present on the status of mainline Linux for RISC-V.
I am super excited already. \o/

Automatic Microarchitecture-Aware Custom Instruction Design for RISC-V Processors
Evgenii Rezunov, Niko Zurstra{\ss}en, Lennart M. Reimann, Rainer Leupers
https://arxiv.org/abs/2509.15782

Automatic Microarchitecture-Aware Custom Instruction Design for RISC-V Processors
An Application-Specific Instruction Set Processor(ASIP) is a specialized microprocessor that provides a trade-off between the programmability of a General Purpose Processor (GPP) and the performance and energy-efficiency of dedicated hardware accelerators. ASIPs are often derived from off-the-shelf GPPs extended by custom instructions tailored towards a specific software workload. One of the most important challenges of designing an ASIP is to find said custom instructions that help to increase…

Crosslisted article(s) found for cs.AR. https://arxiv.org/list/cs.AR/new
[1/1]:
- Decentor-V: Lightweight ML Training on Low-Power RISC-V Edge Devices
Marcelo Ribeiro, Diogo Costa, Gon\c{c}alo Moreira, Sandro Pinto, Tiago Gomes

Crosslisted article(s) found for cs.AR. https://arxiv.org/list/cs.AR/new
[1/1]:
- MaRVIn: A Cross-Layer Mixed-Precision RISC-V Framework for DNN Inference, from ISA Extension to H...
Giorgos Armeniakos, Alexis Maras, Sotirios Xydis, Dimitrios Soudris