Poking around a bit more at the PCIe configuration on my storage cluster nodes and between the UEFI config and the manual I think I fully understand the topology now.
(do consumer mainboards ever publish this kind of info? I'm gonna guess no... but I havent bought one in ~10 years)
The CPU itself has 48 PCIe lanes, which was the most available when I deployed these (icelake-SP bumped this up to 64, and sapphire rapids to 80).
They're divided into three x16 root comp…